CY8C52_1106 Datasheet, PDF (19/95 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 40 MHz operation

PRELIMINARY
PSoC^® 5: CY8C52 Family Datasheet
3-24 MHz
IMO
4-25 MHz
ECO
Figure 6-1. Clocking Subsystem
External IO
or DSI
0-40 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
48 MHz
Doubler for
USB
24-40 MHz
PLL
System
Clock Mux
Bus Clock Divider
16 bit
Bus
Clock
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
7
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
6.1.1 Internal Oscillators
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±4% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±4% at 3 MHz, up to ±10% at 24 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see USB
Clock Domain). The IMO provides clock outputs at 3, 6, 12, and
24 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time. The PLL block provides
a mechanism for generating clock frequencies based upon a
variety of input sources. The PLL outputs clock frequencies in
the range of 24 to 40 MHz. Its input and feedback dividers supply
4032 discrete ratios to create almost any desired system clock
frequency. The accuracy of the PLL output depends on the
accuracy of the PLL input source. The most common PLL use is
to multiply the IMO clock at 3 MHz, where it is most accurate, to
generate the CPU and system clocks up to the device’s
maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 KHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW). The central
timewheel is a 1 KHz, free-running, 13-bit counter clocked by the
ILO. The central timewheel is always enabled except in
hibernate mode and when the CPU is stopped during debug on
chip mode. It can be used to generate periodic interrupts for
timing purposes or to wake the system from a low power mode.
Firmware can reset the central timewheel.
Document Number: 001-66236 Rev. *A
Page 19 of 95