Z9974 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9974
Maximum Ratings^[2]
Maximum Input Voltage Relative to V_SS: ............. V_SS – 0.3V
Maximum Input Voltage Relative to V_DD:............. V_DD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum Power Supply: ................................................5.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V_in and V_out should be constrained to the
range:
V_SS < (V_in or V_out) < V_DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V_SS or V_DD).
DC Parameters V_DD = 3.3V ±5%, T_A = –40°C to +85°C
Parameter
Description
Conditions
V_IL
V_IH
I_IL
I_IH
V_OL
V_OH
I_DDQ
Cin
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Capacitance
I_OL = 20 mA
I_OH = –20 mA
per input
Min.
V_SS
2.0
2.4
Typ.
20
Max.
0.8
V_DD
–100
100
0.5
8
Unit
V
V
µA
µA
V
V
mA
pF
AC Parameters^[3] V_DD = 3.3V ±5%, T_A = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
T_LOCK
Maximum PLL Lock Time
Stable power supply & valid clocks
presented on TCLK(0:1) pins
10
ms
F_VCO
VCO Lock Range
FselFB(0:1)=/4 to /12
200
T_inr,T_inf
TCLK(0:1) Input Rise/Fall
Time
500
MHz
3
ns
F_REF
F_REFpw
T_pw
Input Reference Frequency
Input Reference Duty Cycle
Output Duty Cycle
Measured at V_DD/2
Note 4
Note 4
Tcycle/2
– 800
Tcycle/2
± 500
Note 4
Note 4
Tcycle/2
+ 800
MHz
%
ps
T_r,T_f
Rise Time/Fall Time
Measured between 0.8V and 2.0V 0.15
1.5
ns
Z_o
Output Impedance
7
10
Ω
T_s
Output to Output Skew
All outputs equally loaded
250
ps
T_pd
Propagation Delay, TCLK(0:1) Measured at 50 MHz, V_DD/2
–250
to FBIN
100
ps
T_j
T_PLZ, T_PHZ
T_PZL
F_out
Cycle to Cycle Jitter
Output Disable Time
Output Enable Time
Maximum Output Frequency
Measured at 50 MHz, V_DD/2
After MR# goes LOW
After MR# goes HIGH
Q (/2)
Q (/4)
±100
ps
2
10
ns
2
10
ns
125
MHz
62
Q (/6)
41
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Z9974 outputs can
drive series or parallel terminator 50Ω (or 50Ω to V_DD/2).
4. Input Reference Frequency is limited by the divider selection and the VCO lock range.
Document #: 38-07090 Rev. *C
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