Z9974 Datasheet, PDF (2/7 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9974
Block Diagram
fsela
TCLK_sel
250K
250K
VDD
250K
0
TCLK0
1
TCLK1
250K
FB_In
PLL_EN
VCO_sel
fselb
fselc
fselFB1
fselFB0
OE
MR#
VDD
250K
VDD
250K
250K
250K
250K
250K
250K
VDD
250K
VDD
250K
PLL
Ref-in
0
VCO-out
1
Feedback
0
C /2
1
/4
Reset#
Divide by
2&4
Table 1. Feedback Divider Selection
VCO_Sel
0
0
0
0
1
1
Inputs
fselFB0
0
0
1
1
0
0
1
1
1
1
Table 2. Output Divider Selection
VCO_Sel
fsela
0
0
0
1
1
0
1
1
Qa
VCO/4
VCO/8
VCO/8
VCO/16
0
1
0
1
C /2
/4
/6
0
Reset#
1
Divide by
2, 4 & 6
0
0
1
C
1
/2
Reset#
Div. by 2
fselFB1
0
1
0
1
0
1
0
1
fselb
0
1
0
1
Qb
VCO/4
VCO/8
VCO/8
VCO/16
Document #: 38-07090 Rev. *C
A _{AND Y}
5
Gate
5
B
5
Qa(0:4)
A _AND
Gate ^Y
5
5
B
5
A _AND
Gate ^Y
4
4
B
4
Qb(0:4)
Qc(0:3)
1
QFB
Output
QFB
VCO/8
VCO/12
VCO/16
VCO/24
VCO/16
VCO/24
VCO/32
VCO/48
fselC
0
1
0
1
Qc
VCO/8
VCO/12
VCO/16
VCO/24
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