Z9974 Datasheet, PDF (3/7 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9974
Pin Description^[1]
Pin
2
3
Name
MR#
OE
PWR
I/O
I
I
Description
Master Reset pin. Active LOW. It has a 250-KΩ internal pull-up. When forced
LOW, all outputs are three-stated (high impedance) and internal dividers are
reset.
Output Enable pin. Active LOW. It has a 250-KΩ internal pull-up. When forced
LOW, Qa(0:4), Qb(0:4), and Qc(0:3) outputs are stopped in a LOW state. QFB
is not affected by this control signal.
7, 5, 4
6
fsel(a,b, c)
PLL_EN
I
Input select pins for setting the output dividers of Qa(0:4), Qb(0:4), and Qc(0:3)
respectively. Each pin has an internal 250-KΩ pull-down. See Table 2 for output
divide ratios.
I
Input pin for bypassing the PLL. It has an internal 250-KΩ pull-up. When forced
LOW, the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL
and drives the dividers, typically for device testing.
8
TCLK_sel
I
9,10
TCLK(0:1)
I
14,20
fselFB(0:1)
I
16,18,21,23, Qa(0:4)
25
VDDa O
Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel
= 0, TCLK0 is selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a
250-kΩ internal pull-down.
Input pins for applying a reference clock to the PLL. The active input is
selected by TCLK_sel, pin# 8. TCLK0 has a 250-KΩ internal pull-down. TCLK1
has a 250-KΩ internal pull-up.
Input select pins for setting the Feedback divide ratio at QFB output,
pin #29. See Table 1. Each of these pins has a 250-KΩ internal pull-down.
High-drive, low-voltage CMOS, output clock buffers, Bank Qa. Their divide
ratio is programmed by fsela, pin #7.
29
QFB
VDDFB O
31
FB_In
I
32,34,36,48, Qb(0:4)
40
44,46,48,50 Qc(0:3)
VDDb O
VDDc O
52
VCO_Sel
I
Low-voltage CMOS output feedback clock to the internal PLL. The divide
ratio for this output is set by fselFB(0:1). A delay capacitor or trace may be applied
to this pin in order to control the Input Reference/Output Banks phase relation-
ship.
Feedback input pin. Typically connects to the QFB output for accessing the
feedback to the PLL. It has a 250-kΩ internal pull-up.
High-drive, low-voltage CMOS, output clock buffers, Bank Qb. Their divide
ratio is programmed by fselb, pin #4.
High-drive, low-voltage CMOS, output clock buffers, Bank Qc. Their divide
ratio is programmed by fselc, pin #5.
Input select pin for setting the divider of the VCO output. It has a 250-kΩ
internal pull-down. If VCO_sel = 0, then the PLL VCO output is divided by 2. If
VCO_sel = 1, then the PLL VCO output is divided by 4. See Table 1 and Table 2.
11,27,42
n/c
-
These pins are not connected internally. They may be attached to a ground
plane.
12
VDDI
15
VSSI
13
VDDA
P
Power for input logic circuitry.
P
Ground for input logic circuitry.
P
Power and Ground supply pins for internal analog circuitry.
17,22,26
19,24
28
30
33,37,41
VDDa
VSSa
VDDFB
VSSFB
VDDb
P
3.3V supply for Qa(0:4) output bank, and fselFB1 input.
P
Common ground for Qa(0:4) output bank, and fselFB1 input.
P
Power supply pin for QFB output and FB_In input pins and digital circuitry.
P
Ground supply pin for QFB output and FB_In input pins and digital circuitry.
P
3.3V supply for Qb(0:4) output bank.
Note:
1. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins,
their high-frequency filtering characteristic will be cancelled by the lead inductances of the traces.
Document #: 38-07090 Rev. *C
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