Z9974 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9974
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
• Output Frequency up to 125 MHz
• Supports PowerPC^®, and Pentium^® processors
• 15 Clock outputs: frequency configurable
• Two Reference clock inputs for dynamic toggling
• Output Three-State control
• Spread spectrum compatible
• 3.3V power supply
• Pin compatible with MPC974
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Description
The Z9974 is a low-cost 3.3V zero delay clock driver for
high-speed signal buffering and redistribution.
The designer can select various Input/Output Frequency by
setting fsela, fselb, fselc, fselFB(0:1), and VCO_Sel.
The Z9974 integrates PLL technology for zero delay propaga-
tion from input to output. The PLL feedback is externally avail-
able for propagation delay tuning and divide ratio alternatives
as per Table 1.
The Z9974 has three banks of outputs with independent divid-
er stages. These dividers allow the banks to have different
frequencies as per Table 2.
TCLK0 and TCLK1 are selectable input reference clocks and
may be toggled dynamically during operation to provide mod-
ulation and phase shifting designs.
This device includes a Master Reset signal, which disables the
outputs (Hi-Z) mode, and reset all internal digital circuitry (ex-
cluding the PLL).
An Output Enable, OE, input pin is available for disabling the
Qa(0:4), Qb(0:4), and Qc(0:3) outputs and forcing them to
LOW state. All outputs are held LOW with input clock turned
off.
Pin Configuration
VSSA
MR#
OE
fselb
fselc
PLL_EN
fsela
TClk_Sel
TClk0
TClk1
NC
VDDI
VDDA
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
Z9974 ⁶
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSSb
QB1
VDDb
Qb2
VSSb
Qb3
VDDb
Qb4
FB_IN
VSSFB
QFB
VDDFB
NC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07090 Rev. *C
Revised December 21, 2002