Z9951 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Description
The Z9951 has an integrated PLL that provides low skew and low jitter clock outputs for high performance
microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480
MHz. This allows a wide range of output frequencies from 25MHz to 180MHz.
The phase detector compares the input reference clock to the external feedback input. For normal operation, the
external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input
reference clock set by SEL(A:D) select inputs, see Table 2. The VCO frequency is then divided down to provide the
required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.
SELA QA SELB QB SELC QC SELD QD
0
÷2
0
÷4
0
÷4
0
÷4
1
÷4
1
÷8
1
÷8
1
÷8
Table 2
Zero Delay Buffer
When used as a zero delay buffer the Z9951 will likely be in a nested clock tree application. For these applications the
Z9951 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior skew performance. The Z9951 then can lock onto the
LVPECL reference and translate with near zero delay to low skew outputs.
By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock the Tpd of the Z9951 is a function of the configuration used.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
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