Z9951 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Product Features
• 180MHz Clock Support
• Supports PowerPC^TM, Intel and RISC Processors
• 9 Clock Outputs: Frequency Configurable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Output Disable Control
• Spread Spectrum Compatible
• 3.3V Power Supply
• Pin Compatible with MPC951
• Industrial Temp. Range: -40°C to +85°C
• 32-Pin TQFP Package
Block Diagram
SELA
PLL_EN
TCLK
REF_SEL
PECL_CLK
PECL_CLK#
Phase
Detector
VCO
200-
480MHz
2/ 4
QA
LPF
4/ 8
QB
FB_IN
SELB
SELC
MR/OE#
Power-On Reset
SELD
4/ 8
4/ 8
QC0
QC1
QD0
QD1
QD2
QD3
QD4
Frequency Table
SEL (A:D) QA
QB QC (0,1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
Table 1
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
QD (0:4)
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Pin Configuration
VDD 1
FB_IN 2
SELA 3
SELB 4
SELC 5
SELD 6
VSS 7
PECL_CLK 8
Z9951
24 QC0
23 VDDC
22 QC1
21 VSS
20 QD0
19 VDDC
18 QD1
17 VSS
Figure 1
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
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