Z9951 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
AC Parameters¹
SYMBOL
PARAMETER
MIN
TYP
MAX
Tr / Tf
TCLK Input Rise / Fall
3.0
Fref
Reference Input Frequency
Note 2
Note 2
FrefDC
Reference Input Duty Cycle
25
75
Fvco
PLL VCO Lock Range
200
480
Tlock
Maximum PLL lock Time
10
Tr / Tf
Output Clocks Rise / Fall Time^4,5
0.10
1.0
Fout
Maximum Output Frequency
-
180
120
FoutDC
Output Duty Cycle^4,5
TCYCLE/2 –
1
60
TCYCLE/2 + 1
tpZL, tpZH
Output enable time (all outputs)
6
tpLZ, tpHZ
TCCJ
Tpd
TSKEW0
Output disable time (all outputs)
Cycle to Cycle Jitter (peak to peak)^4,5
TCLK to FB_IN Delay³
PECL_CLK to FB_IN Delay³
Any Output to Any Output Skew^4,5
50
-950
-
+/- 100
250
-770
200
7
400
-600
350
VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C
UNITS
ns
MHz
%
MHz
ms
ns
MHz
ns
ns
ns
ps
ps
ps
ps
CONDITIONS
0.8V to 2.0V
QA = (÷2)
QA/QB = (÷4)
QB = (÷8)
Fref = 50MHz,
Feedback = VCO/8
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines.
Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
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