Z9951 Datasheet, PDF (2/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9951
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Pin Description
PIN
NAME
8
PECL_CLK
9
PECL_CLK#
30
TCLK
28
QA
26
QB
22, 24
QC(1,0)
12, 14, 16, QD(4:0)
18, 20
2
FB_IN
10
MR/OE#
PWR I/O
I
I
I
VDDC O
VDDC O
VDDC O
VDDC O
I
I
31
PLL_EN
I
32
REF_SEL
I
3, 4, 5, 6
SEL(A:D)
I
11, 15, 19, VDDC
23, 27
1
VDD
7, 13, 17, 21, VSS
25, 29
PD = Internal Pull-Down, PU = Internal Pull-Up.
TYPE
PU
Description
PECL Input Clock.
PECL Input Clock.
External Test Clock Input.
Clock Output. See Frequency Table.
Clock Output. See Frequency Table.
Clock Outputs. See Frequency Table.
Clock Outputs. See Frequency Table.
PD
Feedback Clock Input. Connect to an output for normal operation.
Master Reset/Output Enable Input. When asserted high, resets
all of the internal flip-flops and also disables all of the outputs.
When pulled low, releases the internal flip-flops from reset and
enables all of the outputs.
PLL Enable Input. When asserted high, PLL is enabled. And
when set low, PLL is bypassed.
Reference Select Input. When high, TCLK is the reference clock
and when low, PECL clock is selected.
Frequency Select Inputs. See Frequency Table.
If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8
If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷4
3.3V Power Supply for Output Clock Buffers.
3.3V Power Supply for PLL
Common Ground
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07084 Rev. *B
12/22/2002
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