CYV15G0403TB Datasheet, PDF (5/21 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Serializer

CYV15G0403TB
Pin Configuration (Top View)^[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC
OUT
C1–
NC
OUT
C2–
V_CC
NC
OUT _{GND GND} OUT _GND OUT _{GND GND} OUT
D1–
D2–
A1–
A2–
V_CC
V_CC
OUT
B1–
V_CC
OUT
B2–
B
V_CC
OUT
C1+
V_CC
OUT
C2+
V_CC
V_CC
OUT _GND
D1+
NC
OUT
D2+
NC
OUT _{GND NC}
A1+
OUT
A2+
V_CC
NC
OUT
B1+
NC
OUT
B2+
C
TDI
TMS _{VCC VCC VCC NC}
NC GND NC
NC
DATA DATA _GND
[3]
[1]
NC
SPD
SELD
V_CC
NC ^TRST GND ^TDO
D
TCLK RESET _VCC
V_CC
V_CC
V_CC
SPD _{GND GND}
SELC
DATA
[4]
DATA
[2]
DATA
[0]
GND
GND
NC
V_CC
NC
NC ^{SCAN TMEN3}
EN2
E
V_CC V_CC V_CC V_CC
V_CC V_CC V_CC V_CC
F
NC NC ^TX NC
DC[0]
G
TX WREN TX
TX
DC[7]
DC[4] DC[1]
H
GND GND GND GND
NC NC ^TX NC
CLKOB
SPD _NC SPD _NC
SELB
SELA
GND GND GND GND
J
TX
TX
TX
TX
DC[9] DC[5] DC[2] DC[3]
K
NC ^{REF TX}
TX
CLKC– DC[8] CLKC
L
NC ^REF NC ^TX
CLKC+
DC[6]
M
NC NC NC ^TX
ERRC
N
GND GND GND GND
NC NC NC NC
NC NC NC NC
NC NC NC ^TX
DB[6]
REF REF TX
TX
CLKB+ CLKB– ERRB CLKB
GND GND GND GND
P
NC NC NC NC
R
NC ^TX NC NC
CLKOC
T
V_CC V_CC V_CC V_CC
TX
TX
TX
TX
DB[5] DB[4] DB[3] DB[2]
TX
TX
TX
TX
DB[1] DB[0] DB[9] DB[7]
V_CC V_CC V_CC V_CC
U
TX
TX
TX
TX
DD[0] DD[1] DD[2] DD[9]
V_CC
NC
NC
GND ^{TX ADDR REF TX} GND ^TX
TX
DA[9] [0] CLKD– DA[1]
DA[4] DA[8]
V_CC
NC ^TX NC
DB[8]
NC
V
TX
TX
TX
NC
DD[3] DD[4] DD[8]
V_CC
NC
NC
GND
NC
ADDR REF TX _GND TX
TX
[2] CLKD+ CLKOA
DA[3] DA[7]
V_CC
NC
NC
NC
NC
W
TX
TX _NC
DD[5] DD[7]
NC
V_CC
NC
NC
GND ^{ADDR ADDR}
[3]
[1]
NC
TX _GND TX
TX
ERRA
DA[2] DA[6]
V_CC
NC ^REF NC
CLKA+
NC
Y
TX
TX _NC
DD[6] CLKD
NC
V_CC
NC
NC
GND ^TX
NC
CLKOD
TX
CLKA
NC
GND ^TX
TX
DA[0] DA[5]
V_CC
TX REF
ERRD CLKA–
NC
NC
Note
1. NC = Do not connect.
Document #: 38-02104 Rev. *C
Page 5 of 21
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