CYV15G0403TB Datasheet, PDF (13/21 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Serializer

CYV15G0403TB
Maximum Ratings
Above which the useful life may be impaired. User guidelines
only, not tested
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to V_CC + 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V_CC + 0.5V
CYV15G0403TB DC Electrical Characteristics
Static Discharge Voltage.......................................... > 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Power-up Requirements
The CYV15G0403TB requires one power-supply. The Voltage
on any input or I/O pin cannot exceed the power pin during
power-up.
Operating Range
Range
Commercial
Ambient Temperature
0°C to +70°C
V_CC
+3.3V ±5%
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
V_OHT
Output HIGH Voltage
V_OLT
Output LOW Voltage
I_OST
Output Short Circuit Current
I_OZL
High-Z Output Leakage Current
LVTTL-compatible Inputs
I_OH = −4 mA, V_CC = Min.
I_OL = 4 mA, V_CC = Min.
V_OUT = 0V^[7], V_CC = 3.3V
V_OUT = 0V, V_CC
2.4
V
0.4
V
–20
–100
mA
–20
20
µA
V_IHT
V_ILT
I_IHT
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
I_ILT
Input LOW Current
I_IHPDT
Input HIGH Current with internal pull-down
I_ILPUT
Input LOW Current with internal pull-up
LVDIFF Inputs: REFCLKx±
V_DIFF[8]
Input Differential Voltage
V_IHHP
Highest Input HIGH Voltage
V_ILLP
Lowest Input LOW voltage
V_COMREF[9] Common Mode Range
3-Level Inputs
REFCLKx Input, V_IN = V_CC
Other Inputs, V_IN = V_CC
REFCLKx Input, V_IN = 0.0V
Other Inputs, V_IN = 0.0V
V_IN = V_CC
V_IN = 0.0V
2.0
–0.5
400
1.2
0.0
1.0
V_CC + 0.3 V
0.8
V
1.5
mA
+40
µA
–1.5
mA
–40
µA
+200
µA
–200
µA
V_CC
mV
V_CC
V
V_CC/2
V
V_CC – 1.2V V
V_IHH
Three-Level Input HIGH Voltage
Min. ≤ V_CC ≤ Max.
0.87 * V_CC
V_CC
V
V_IMM
Three-Level Input MID Voltage
Min. ≤ V_CC ≤ Max.
0.47 * V_CC 0.53 * V_CC V
V_ILL
Three-Level Input LOW Voltage
Min. ≤ V_CC ≤ Max.
0.0
0.13 * V_CC V
I_IHH
Input HIGH Current
V_IN = V_CC
200
µA
I_IMM
Input MID current
V_IN = V_CC/2
–50
50
µA
I_ILL
Input LOW current
V_IN = GND
–200
µA
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
V_OHC
Output HIGH Voltage
(V_cc Referenced)
100Ω differential load
150Ω differential load
V_CC – 0.5 V_CC – 0.2 V
V_CC – 0.5 V_CC – 0.2 V
Notes
7. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
8. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the
true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.
9. The common mode range defines the allowable range of REFCLKx+ and REFCLKx− when REFCLKx+ = REFCLKx−. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02104 Rev. *C
Page 13 of 21
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