CYP15G0403DXB_09 Datasheet, PDF (5/45 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver

Receive Path Block Diagram
SPDSELA
RXPLLPDA
SDASELA[1:0]
LPENA
INSELA
INA1+
INA1–
INA2+
INA2–
TXLBA
ULCA
SPDSELB
RXPLLPDB
SDASELB[1:0]
LPENB
INSELB
INB1+
INB1–
INB2+
INB2–
TXLBB
ULCB
SPDSELC
RXPLLPDC
SDASELC[1:0]
LPENC
INSELC
INC1+
INC1–
INC2+
INC2–
TXLBC
ULCC
SPDSELD
RXPLLPDD
SDASELD[1:0]
LPEND
INSELD
IND1+
IND1–
IND2+
IND2–
TXLBD
ULCD
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
LDTDEN
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
Document #: 38-02065 Rev. *F
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
TXLB[A..D] are Internal Serial Loopback Signals
= Internal Signal
JTAG
Boundary
Scan
Controller
RESET
TRST
TMS
TCLK
TDI
TDO
LFIA
8
RXDA[7:0]
3
RXSTA[2:0]
Clock
Select
÷2
8
3
RXCLKA+
RXCLKA–
LFIB
RXDB[7:0]
RXSTB[2:0]
Clock
Select
÷2
8
3
RXCLKB+
RXCLKB–
LFIC
RXDC[7:0]
RXSTC[2:0]
Clock
Select
÷2
8
3
RXCLKC+
RXCLKC–
LFID
RXDD[7:0]
RXSTD[2:0]
Clock
Select
÷2
RXCLKD+
RXCLKD–
Page 5 of 45
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