CYP15G0403DXB_09 Datasheet, PDF (33/45 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver

CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP(V)(W)15G0403DXB HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
TXCLKOx Timing
TXRATEx = 0
REFCLKx
TXCLKOx
Note37
t_REFCLK
t_REFH
Note36
t_REFL
t_TXOH
t_TXCLKO
t_TXOL
Switching Waveforms for the CYP(V)(W)15G0403DXB HOTLink II Receiver
Receive Interface
Read Timing
REFCLKx Selected
Full-rate RXCLKx±
REFCLKx
RXDx[7:0],
RXSTx[2:0],
TXERRx^[39]
RXCLKx
t_REFH
t_REFCLK
t_REFL
t_RREFDA
t_RREFDW
t_REFxDV+
t_RREFDW
t_REFxDV–
Receive Interface
Read Timing
REFCLKx Selected
Half-rate RXCLKx±
REFCLKx
RXDx[7:0],
RXSTx[2:0],
TXERRx^[39]
t_REFH
t_REFCLK
t_RREFDA
t_RREFDW
t_REFxDV+
t_REFL
t_RREFDA
t_RREFDW
t_REFxDV–
RXCLKx
Note 38
Notes
38. When operated with a half-rate REFCLKx±, the set-up and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the
respective clock output
39. TXERRx is synchronous to RXCLKx only when RXCLKx is selected as REFCLK.
Document #: 38-02065 Rev. *F
Page 33 of 45
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