CYP15G0403DXB_09 Datasheet, PDF (28/45 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver

CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP(V)(W)15G0403DXB DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
V_OHC
V_OLC
V_ODIF
Output HIGH Voltage
(V_cc Referenced)
Output LOW Voltage
(V_CC Referenced)
Output Differential Voltage
|(OUT+) − (OUT−)|
100Ω differential load
150Ω differential load
100Ω differential load
150Ω differential load
100Ω differential load
150Ω differential load
V_CC – 0.5
V_CC – 0.5
V_CC – 1.4
V_CC – 1.4
450
560
V_CC – 0.2 V
V_CC – 0.2 V
V_CC – 0.7 V
V_CC – 0.7 V
900
mV
1000
mV
Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2±
V_DIFFs[11]
Input Differential Voltage |(IN+) − (IN−)|
100
1200
mV
V_IHE
Highest Input HIGH Voltage
V_CC
V
V_ILE
Lowest Input LOW Voltage
V_CC – 2.0
V
I_IHE
Input HIGH Current
V_IN = V_IHE Max.
1350
μA
I_ILE
VI_COM[13]
Input LOW Current
Common Mode input range
V_IN = V_ILE Min.
((V_CC – 2.0V)+0.5)min,
(V_CC – 0.5V) max.
–700
+1.25
μA
+3.1
V
Power Supply
Typ.
Max.
I_CC ^{[14, 15]}
Max Power Supply Current
REFCLKx = Commercial
MAX
Industrial
910
1270
mA
1320
mA
I_CC ^{[14, 15]}
Typical Power Supply Current
REFCLKx = Commercial
125 MHz _Industrial
900
1270
mA
1320
mA
AC Test Loads and Waveforms
3.3V
R1
R1 = 590Ω
R2 = 435Ω
C_L ≤ 7 pF
C_L
(Includes fixture and
R2
probe capacitance)
[16]
(a) LVTTL Output Test Load
3.0V
V_th = 1.4V
GND
2.0V
0.8V
2.0V
0.8V
V_th = 1.4V
≤ 1 ns
≤ 1 ns
(c) LVTTL Input Test Waveform^[17]
R_L = 100Ω
R_L
(Includes fixture and
probe capacitance)
[16]
(b) CML Output Test Load
V_IHE
V_ILE
20%
≤ 270 ps
80%
V_IHE
80%
V_ILE
20%
≤ 270 ps
(d) CML/LVPECL Input Test Waveform
Notes
13. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
14. Maximum I_CC is measured with V_CC = MAX, RFENx = 0, T_A = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01
pattern, and outputs unloaded.
15. Typical I_CC is measured under similar conditions except with V_CC = 3.3V, T_A = 25°C, RFENx = 0, with all channels enabled and one Serial Line Driver per transmit
channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
16. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
17. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
Document #: 38-02065 Rev. *F
Page 28 of 45
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