CYP15G0403DXB_09 Datasheet, PDF (32/45 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II Transceiver

CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP(V)(W)15G0403DXB HOTLink II Transmitter Switching Waveforms
Transmit Interface
Write Timing
TXCLKx selected
TXCLKx
TXDx[7:0],
TXCTx[1:0],
t_TXCLK
t_TXCLKH
t_TXCLKL
t_TXDS
t_TXDH
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 0
REFCLKx
TXDx[7:0],
TXCTx[1:0],
Transmit Interface
Write Timing
REFCLKx selected
TXRATEx = 1
REFCLKx
TXDx[7:0],
TXCTx[1:0],
t_REFH
t_REFCLK
t_REFL
t_TREFDS
t_TREFDH
t_REFH
t_REFCLK
Note 35
t_TREFDS
t_REFL
t_TREFDH ^tTREFDS
t_TREFDH
Transmit Interface
TXCLKOx Timing
TXRATEx = 1
REFCLKx
Note 37
t_REFH
t_TXCLKO
t_REFCLK
Note 36
t_REFL
TXCLKOx
(internal)
Notes
35. When REFCLKx± is configured for half-rate operation (TXRATE = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using
both the rising and falling edges of REFCLKx.
36. The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLKx±.
37. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx± input.
Document #: 38-02065 Rev. *F
Page 32 of 45
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