CY7C43646 Datasheet, PDF (5/39 Pages) Cypress Semiconductor – 1K/4K/16K x36/x18/x2 Tri Bus FIFO

CY7C43646
CY7C43666
CY7C43686
Pin Definitions (continued)
Signal Name Description
FS1/SEN
Flag Offset
Select 1/Serial
Enable
FS0/SD
Flag Offset
Select 0/Serial
Data
MBA
Port A Mailbox
Select
MBB
MBC
MBF1
MBF2
MRS1
Port B Mailbox
Select
Port C Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
MRS2
FIFO2 Master
Reset
PRS1
PRS2
RENB
RT1
FIFO1 Partial
Reset
FIFO2 Partial
Reset
Port B Read
Enable
FIFO1
Retransmit
I/O
Function
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
I
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, or serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 32 for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the
CY7C43666, and 56 for the CY7C43686. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
I A HIGH level on MBA chooses a mailbox register for a Port A read or write
operation. When a read operation is performed on Port A, a HIGH level on MBA selects
data from the Mail2 register for output and a LOW level selects FIFO2 output register
data for output. When a write operation is performed on Port A, a High level on MBA
will write the data into Mail 1 register, while a Low level will write the data into FIFO 1.
I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When
a read operation is performed on Port B, a HIGH level on MBB selects data from the
Mail1 register for output and a LOW level selects FIFO1 output register data for output.
I When a write operation is performed on Port C, a HIGH level on MBC writes data
into Mail2 register, and a LOW level writes into FIFO2.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable
flag default offsets for FIFO1. It also configures Port B for bus size and endian
arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transi-
tions of CLKB must occur while MRS1 is LOW.
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2
selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2
is LOW.
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location
of memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on
Port B.
I A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
Document #: 38-06023 Rev. *C
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