CY7C43646 Datasheet, PDF (28/39 Pages) Cypress Semiconductor – 1K/4K/16K x36/x18/x2 Tri Bus FIFO

CY7C43646
CY7C43666
CY7C43686
Switching Waveforms (continued)
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)^{[43, 44]}
CLKC
MBC
t_ENS t_ENH
t_CLK
t_CLKH t_CLKL
WENC
t_ENS t_ENH
FFC/IRC ^HIGH
t_DS t_DH
C_0–17
W1a
CLKA
EFA/ORA FIFO2 Empty
W1b
t_SKEW1[45] ^tCLKH ^tCLKL
t_CLK
CSA
LOW
W/RA
LOW
MBA
ENA
LOW
A_0–35
Old Data in FIFO2 Output Register
t_REF
t_REF
t_ENSt_ENH
t_A
W1
Notes:
43. SIZEC = LOW; If BE = HIGH, W1a is the most significant word, W1b is the least significant word. If BE = LOW, W1a is the least significant word, W1b is the most
significant word.
44. If SIZEC = HIGH (byte size), t_SKEW1 is referenced to the rising CLKC edge that writes the last byte of the long word.
45. t_SKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than t_SKEW1, then the transition of ORA HIGH and load of
the first word to the output register may occur one CLKA cycle later than shown.
Document #: 38-06023 Rev. *C
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