CY7C43646 Datasheet, PDF (1/39 Pages) Cypress Semiconductor – 1K/4K/16K x36/x18/x2 Tri Bus FIFO

CY7C43666 CY7C436461K/4K/16K x36/x18/x2 Tri Bus FIFO
CY7C43646
CY7C43666
CY7C43686
1K/4K/16K x36/x18/x2 Tri Bus FIFO
Features
• High-speed, low-power, first-in first-out (FIFO) memo-
ries w/ three independent ports (one bidirectional x36,
and two unidirectional x18)
• 1K x36/x18x2 (CY7C43646)
• 4K x36/x18x2 (CY7C43666)
• 16K x36/x18x2 (CY7C43686)
• 0.35-micron CMOS for optimum speed/power
• High speed 133-MHz operation (7.5-ns read/write
cycle times)
• Low power
— I_CC= 100 mA
— I_SB= 10 mA
Logic Block Diagram
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT mode user-selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A_0−35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MBF2
Mail1
Register
1K/4K/16K
x36
Dual Ported
Memory
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Read
Pointer
Write
Pointer
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail2
Register
MBF1
Port B
Control
Logic
B_0−17
CLKB
RENB
CSB
SIZEB
MBB
RTI
Common
Port Logic
(B and C)
FIFO2,
Mail2
Reset
Logic
Port C
Control
Logic
EFB/ORB
AEB
BE
BE/FWFT
FFC/IRC
AFC
MRS2
PRS2
C_0−17
CLKC
WENC
SIZEC
MBC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06023 Rev. *C
Revised September 26, 2003