C9531_04 Datasheet, PDF (5/10 Pages) Cypress Semiconductor – PCIX I/O System Clock Generator with EMI Control Features

C9531
Byte 2: PCI Register (continued)
Bit
@Pup
3
1
Name
19
2
1
22
1
1
23
0
1
24
CLK3 Output Enable
0 = Disable, 1= Enable
CLK2Output Enable
0 = Disable, 1= Enable
CLK1 Output Enable
0 = Disable, 1= Enable
CLK0 Output Enable
0 = Disable, 1= Enable
Description
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state
condition by bringing their relevant OE pins to a logic low state.
This transition to and from a three-state and active condition
is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus
control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
The output enable pin contains an internal pull-up resistor that
will insure that a logic 1 is maintained and sensed by the
device if no external circuitry is connected to this pin.
Output Clock Frequency Control
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 bits 3 and 4 to control
the output clock’s frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal.
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
C_L =
(C_XINPCB + C_XINFTG + C_XINDISC) x (C_XOUTPCB) + C_XOUTFTG) + C_XOUTDISC)
(C_XINPCB + C_XINFTG + C_XINDISC) + (C_XOUTPCB) + C_XOUTFTG) + C_XOUTDISC)
where:
C_XTAL = The load rating of the crystal.
C_XINFTG = The clock generators XIN pin effective device internal capacitance to ground.
C_XOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground.
C_XINPCB = The effective capacitance to ground of the crystal to device PCB trace.
C_XOUTPCB = The effective capacitance to ground of the crystal to device PCB trace.
C_XINDISC = Any discrete capacitance that is placed between the XIn pin and ground.
C_XOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
C_XINPCB
C_XINDISC
XIN
C_XINFTG
C_XOUTPCB
C_XOUTDISC
XOUT ^CXOUTFTG
Clock Generator
Document #: 38-07034 Rev. *E
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