C9531_04 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – PCIX I/O System Clock Generator with EMI Control Features

C9531
Pin Description^[3]
Pin^[2]
Name
3
XIN
4
XOUT
1
REF
14*
OE
24, 23, 22, 19, 18 CLK(0:4)
8
GOOD#
6*, 7*
S(0,1)
20, 25
10*, 11*, 12*
15*
VDDP
IA(0:2)
SSCG#
28
27
13, 17
2
5, 9, 16, 21, 26
SDATA
SCLK
VDDA
VDD
VSS
PWR^[4]
VDDA
VDDA
VDD
VDD
VDDP
VDD
VDD
VDD
VDD
VDD
VDD
I/O
I
O
O
I
O
O
I
PWR
I
I
I/O
I
I
PWR
PWR
Description
Crystal Buffer Input Pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer Output Pin. Connects to a crystal only. When a Can
Oscillator is used or in test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz.
Output Enable for Clock Bank. Causes the CLK (0:4) output clocks
to be in a three-state condition when driven to a logic low level.
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This
output is latched.
Clock Bank Selection Bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks CLK (0:4).
SMBus Address Selection Input Pins. See Table 3 on page 3.
Spread Spectrum Clock Generator. Enables Spread Spectrum clock
modulation when at a logic low level, see Spread Spectrum Clocking
on page 6.
Data for the Internal SMBus Circuitry. See Table 3 on page 3.
Clock for the Internal SMBus Circuitry. See Table 3 on page 3.
Power for Internal Analog Circuitry. This supply should have a
separately decoupled current source from VDD.
Power supply for internal core logic.
Ground pins for the device.
Notes:
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3. A bypass capacitor (0.1µF) should be placed as close as possible to each V_DD pin. If these bypass capacitors are not close to the pins their high frequency filtering
characteristic will be cancelled by the lead inductance of the trace.
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Document #: 38-07034 Rev. *E
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