C9531_04 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – PCIX I/O System Clock Generator with EMI Control Features

C9531
Serial Control Registers
Byte 0: Output Register
Bit
@Pup
7
1
6
0
5
1
4
0
3
0
2
0
1
0
0
1
Name
TESTEN
SSEN
SSSEL
S1
S0
HWSEL
Description
Test Mode Enable.
1 = Normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
Not used
Not used
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
1
1
Byte0, bit5
0
1
0
1
Description
Frequency generated from second PLL
Frequency generated from XIN
Spread @ –1.0%
Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Frequency
CLK
XIN/4
Outputs
REF
XIN
Note
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit
@Pup
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Name
REFEN
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 2: PCI Register
Bit
@Pup
7
1
6
1
5
1
4
1
Name
18
Reserved
Reserved
Reserved
CLK4 Output Enable
0 = Disable, 1= Enable
Description
Document #: 38-07034 Rev. *E
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