CY8C55_11 Datasheet, PDF (44/112 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C55 Family Datasheet
7.9 Digital Filter Block
Some devices in the CY8C55 family of devices have a dedicated
HW accelerator block used for digital filtering. The DFB has a
dedicated multiplier and accumulator that calculates a 24-bit by
24-bit multiply accumulate in one system clock cycle. This
enables the mapping of a direct form FIR filter that approaches
a computation rate of one FIR tap for each clock cycle. The MCU
can implement any of the functions performed by this block, but
at a slower rate that consumes significant MCU bandwidth.
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
Figure 7-23. DFB Application Diagram (pwr/gnd not shown)
BUSCLK
Digital
Routing
Digital Filter
Block
read_data
write_data
addr
System
Bus
DMA
Request
DMA
CTRL
Data
Source
(PHUB)
Data
Dest
(PHUB)
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
■ Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
■ High resolution Delta-Sigma ADC
■ Two successive approximation (SAR) ADCs
■ Four 8-bit DACs that provide either voltage or current output
■ Four comparators with optional connection to configurable LUT
outputs
■ Four configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
■ Four opamps for internal use and connection to GPIO that can
be used as high current output buffers
■ CapSense subsystem to enable capacitive touch sensing
■ Precision reference for generating an accurate analog voltage
for internal analog blocks
Document Number: 001-66235 Rev. **
Page 44 of 112
[+] Feedback