CY8C55_11 Datasheet, PDF (3/112 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C55 Family Datasheet
1. Architectural Overview
Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
4- 25 MHz
( Optional)
32.768 KHz
( Optiona)l
System Wide
Resources
Xtal
Osc
IMO
RTC
Timer
WDT
and
Wake
ILO
Clocking System
Power Management
System
POR and
LVD
Sleep
Power
1.8 V LDO
SMP
Digital Interconnect
Analog Interconnect
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit Quadrature Decoder
Timer
UDB
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
UDB
UART
UDB
UDB
12- Bit SPI
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
Logic
UDB
12- Bit PWM
UDB
UDB
UDB
UDB
UDB
CAN
2.0
I2C
Master/
Slave
4x
Timer
Counter
PWM
FS USB
2.0
System Bus
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3 CPU
Interrupt
Controller
EMIF
FLASH
Cache
Controller
PHUB
DMA
Program &
Debug
Program
Debug &
Trace
Boundary
Scan
LCD Direct
Drive
Digital
Filter
Block
4 x SC / CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
CapSense
4x DAC
Analog System
ADCs
2x
SAR
ADC
1x
Del Sig
ADC
+
4x
Opamp
-
+
4x
CMP
-
USB
PHY
22 Ω
3 per
Opamp
0. 5 to5.5 V
( Optiona)l
Document Number: 001-66235 Rev. **
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