CY7C63221 Datasheet, PDF (44/50 Pages) Cypress Semiconductor – Low-speed USB Peripheral Controller

FOR
FOR
enCoRe™ USB
CY7C63221/31A
24.0 Switching Characteristics
Parameter
Description
Internal Clock Mode
F_ICLK
F_ICLK2
Internal Clock Frequency
Internal Clock Frequency, USB
mode
Min.
5.7
5.91
Max.
Unit
Conditions
6.3
MHz Internal Clock Mode enabled
6.09
MHz Internal Clock Mode enabled, Bit 2 of
register 0xF8h is set (Precision USB
Clocking)^[12]
T_CYC
T_CH
T_CL
t_START
t_WAKE
t_WATCH
T_R
T_R
T_F
T_F
T_RFM
V_CRS
External Oscillator Mode
Input Clock Cycle Time
164.2
169.2
Clock HIGH Time
Clock LOW Time
Reset Timing
Time-out Delay after LVR/BOR
Internal Wake-up Period
WatchDog Timer Period
0.45 t_CYC
0.45 t_CYC
24
60
1
5
10.1
14.6
USB Driver Characteristics
Transition Rise Time
75
Transition Rise Time
300
Transition Fall Time
75
Transition Fall Time
300
Rise/Fall Time Matching
80
125
Output Signal Crossover
Voltage^[17]
1.3
2.0
ns USB Operation, with External ±1.5%
Ceramic Resonator or Crystal
ns
ns
ms
ms Enabled Wake-up Interrupt^[13]
ms F_OSC = 6 MHz
ns CLoad = 200 pF (10% to 90%^[4])
ns CLoad = 600 pF (10% to 90%^[4])
ns CLoad = 200 pF (10% to 90%^[4])
ns CLoad = 600 pF (10% to 90%^[4])
%
t_r/t_f[4, ^14]
V CLoad = 200 to 600 pF^[4]
T_DRATE
T_DJR1
T_DJR2
T_DEOP
T_EOPR2
T_EOPT
T_UDJ1
T_UDJ2
T_LST
USB Data Timing
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP transition Skew
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Width of SE0 during Diff. Transition
1.4775
–75
–45
–40
670
1.25
–95
–150
1.5225
75
45
100
1.50
95
150
210
Mb/s
ns
ns
ns
ns
µs
ns
ns
ns
Ave. Bit Rate (1.5 Mb/s ±1.5%)
To Next Transition^[15]
For Paired Transitions^[15]
Note 15
Accepts as EOP^[15]
To next transition, Figure 24-5
To paired transition, Figure 24-5
T_FPS2
Non-USB Mode Driver
Characteristics
SDATA / SCK Transition Fall Time 50
Note 16
300
ns CLoad = 150 pF to 600 pF
Notes:
12. Initially F_ICLK2=F_ICLK until a USB packet is received.
13. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)
14. Tested at 200 pF.
15. Measured at cross-over point of differential data signals.
16. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.
17. Per the USB 2.0 Specification, Table 7.7, Note 10, the first transition from the Idle state is excluded.
Document #: 38-08028 Rev. *B
Page 44 of 50
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