CY7C63221 Datasheet, PDF (21/50 Pages) Cypress Semiconductor – Low-speed USB Peripheral Controller

FOR
FOR
enCoRe™ USB
CY7C63221/31A
Bit #
7
Bit Name
Read/Write
-
Reset
0
6
5
4
3
2
Reserved
-
-
-
-
-
0
0
0
0
0
Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)
1
0
P1[1:0] Mode1
W
W
0
0
Bit [7:2]: Reserved
Bit [1:0]: P1[1:0] Mode 1
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Each pin can be independently configured as high-impedance inputs, inputs with internal pull-ups, open drain outputs, or tradi-
tional CMOS outputs with selectable drive strengths.
The driving state of each GPIO pin is determined by the value written to the pin’s Data Register and by its associated Mode0 and
Mode1 bits. Table 12-1 lists the configuration states based on these bits. The GPIO ports default on reset to all Data and Mode
Registers cleared, so the pins are all in a high-impedance state. The available GPIO output drive strength are:
• Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
Q1, Q2, and Q3 (Figure 12-1) are OFF. The GPIO pin is not driven internally. Performing a read from the Port Data Register
return the actual logic value on the port pins.
• Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 2 mA of current.
• Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 8 mA of current.
• High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 50 mA of current.
• High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s Data Register = 1)
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of sourcing 2 mA of current.
• Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 1)
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14-kΩ resistor.
Note that open drain mode can be achieved by fixing the Data and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See Section 23.0 for the input threshold voltage in TTL or CMOS
modes). Both input modes include hysteresis to minimize noise sensitivity. In suspend mode, if a pin is used for a wake-up
interrupt using an external R-C circuit, CMOS mode is preferred for lowest power.
Table 12-1. Ports 0 and 1 Output Control Truth Table
Data Register
Mode1
Mode0
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Output Drive Strength
Hi-Z
Hi-Z
Medium (8 mA) Sink
High Drive
Low (2 mA) Sink
Resistive
High (50 mA) Sink
High Drive
Input Threshold
CMOS
TTL
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
12.1 Auxiliary Input Port
Port 2 serves as an auxiliary input port as shown in Figure 12-8. The Port 2 inputs all have TTL input thresholds.
Document #: 38-08028 Rev. *B
Page 21 of 50
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