CY7C63221 Datasheet, PDF (35/50 Pages) Cypress Semiconductor – Low-speed USB Peripheral Controller

FOR
FOR
enCoRe™ USB
CY7C63221/31A
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Figure 19-6 and Figure 19-7 control the interrupt polarity of each GPIO pin.
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0 Interrupt Polarity
Read/Write
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Figure 19-6. Port 0 Interrupt Polarity Register (Address 0x06)
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Bit #
7
Bit Name
Read/Write
-
Reset
0
6
5
4
3
2
Reserved
-
-
-
-
-
0
0
0
0
0
Figure 19-7. Port 1 Interrupt Polarity Register (Address 0x07)
Bit [7:0]: P1[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
1
0
P1[1:0] Interrupt Polarity
W
W
0
0
GPIO
Pin
Port Bit Interrupt
Polarity Register
M
U
X
OR Gate
(1 input per
GPIO pin)
GPIO Interrupt
Flip Flop
1D Q
CLR
1 = Enable
0 = Disable
IRA
Port Bit Interrupt
Enable Register
1 = Enable
0 = Disable
Global
GPIO Interrupt
Enable
(Bit 6, Register 0x20)
Figure 19-8. GPIO Interrupt Diagram
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
Document #: 38-08028 Rev. *B
Page 35 of 50
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