W40S11-02 Datasheet, PDF (4/11 Pages) Cypress Semiconductor – SDRAM Buffer - 2 DIMM (Mobile)

W40S11-02
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 2 gives the bit formats for registers located in Data Bytes
0–6.
Table 2. Data Bytes 0–2 Serial Configuration Map^[2]
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
N/A
Reserved (Reserved)
--
--
6
N/A
Reserved (Reserved)
--
--
5
N/A
Reserved (Reserved)
--
--
4
N/A
Reserved (Reserved)
--
--
3
7
SDRAM3 Clock Output Disable
Low
Active
2
6
SDRAM2 Clock Output Disable
Low
Active
1
3
SDRAM1 Clock Output Disable
Low
Active
0
2
SDRAM0 Clock Output Disable
Low
Active
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
27
SDRAM7 Clock Output Disable
Low
Active
6
26
SDRAM6 Clock Output Disable
Low
Active
5
23
SDRAM5 Clock Output Disable
Low
Active
4
22
SDRAM4 Clock Output Disable
Low
Active
3
N/A
Reserved (Reserved)
--
--
2
N/A
Reserved (Reserved)
--
--
1
N/A
Reserved (Reserved)
--
--
0
N/A
Reserved (Reserved)
--
--
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
7
18
SDRAM9 Clock Output Disable
Low
Active
6
11
SDRAM8 Clock Output Disable
Low
Active
5
N/A
Reserved (Reserved)
--
--
4
N/A
Reserved (Reserved)
--
--
3
N/A
Reserved (Reserved)
--
--
2
N/A
Reserved (Reserved)
--
--
1
N/A
Reserved (Reserved)
--
--
0
N/A
Reserved (Reserved)
--
--
Note:
2. At power-up all SDRAM outputs are enabled and active. It is recommended to program Bits 4–7 of Byte0 and Bits 0–3 of Byte1 to a “0” to save power and reduce
noise.
4