W40S11-02 Datasheet, PDF (2/11 Pages) Cypress Semiconductor – SDRAM Buffer - 2 DIMM (Mobile)

W40S11-02
Pin Definitions
Pin Name
SDRAM0:9
BUF_IN
SDATA
Pin
No.
2, 3, 6, 7,
22, 23, 26,
27, 11, 18
9
14
SCLOCK
15
VDD
GND
OE
1, 5, 10, 13,
19, 24, 28
4, 8, 12, 16,
17, 21, 25
20
Pin
Type
O
I
I/O
I
P
G
I
Pin Description
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled
to within ± 250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
I²C Data Input: Data should be presented to this input as described in the I²C section
of this data sheet. Internal 250-kΩ pull-up resistor.
I²C Clock Input: The I²C Data clock should be presented to this input as described
in the I²C section of this data sheet. Internal 250-kΩ pull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection: Connect all ground pins to the common system ground plane.
Output Enable: Internal 250-kΩ pull-up resistor. Three-states outputs when LOW.
2