W40S11-02 Datasheet, PDF (3/11 Pages) Cypress Semiconductor – SDRAM Buffer - 2 DIMM (Mobile)

W40S11-02
Functional Description
Output Control Pins
Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in phase with BUF_IN but are phase delayed by 1
to 5 ns. Outputs can also be controlled via the I²C interface.
Table 1. Byte Writing Sequence
Output Drivers
The W40S11-02 output buffers are CMOS type which deliver
a rail-to-rail (GND to V_DD) output voltage swing into a nominal
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15 ohms.
Operation
Data is written to the W40S11-02 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Byte
Sequence
1
Byte Name
Slave Address
2
Command
Code
3
Byte Count
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Bit Sequence
11010010
Don’t Care
Don’t Care
Refer to Table 2
Don’t Care
Byte Description
Commands the W40S11-02 to accept the bits in Data Bytes 0–6 for in-
ternal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-02
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W40S11-02, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W40S11-02, therefore bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
The data bits in these bytes set internal W40S11-23 registers that control
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 2, Data Byte Serial Configuration Map.
Refer to Cypress clock drivers.
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