CY8CLED16P01 Datasheet, PDF (35/58 Pages) Cypress Semiconductor – Powerline Communication Solution Integrated Powerline Modem PHY

CY8CLED16P01
10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C  T_A  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 10-13. AC Chip-Level Specifications
Symbol
Description
Min Typ
Max
F_IMO24
Internal Main Oscillator Frequency for 24 MHz 23.4 24
24.6
F_IMO6
Internal Main Oscillator Frequency for 6 MHz 5.5
6
6.5^[6]
F_CPU1
F_48M
F_32K1
F_32K2
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0.0914 24
24.6^[6]
0
48 49.2^{[6, 7]}
15
32
64
– 32.768
–
F_{32K_U}
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
5
–
100
F_PLL
PLL Frequency
– 23.986
–
T_PLLSLEW
PLL Lock Time
0.5
–
10
T_PLLSLEWLOW PLL Lock Time for Low Gain Setting
0.5
–
50
T_OS
External Crystal Oscillator Startup to 1%
–
250
500
T_OSACC
External Crystal Oscillator Startup to 100 ppm –
300
600
T_XRST
External Reset Pulse Width
SR_{POWER_UP} Power Supply Slew Rate
10
–
–
–
–
250
T_POWERUP Time from End of POR to CPU Executing Code –
16
100
DC24M
24 MHz Duty Cycle
40
50
60
Units
MHz
MHz
MHz
MHz
kHz
kHz
kHz
MHz
ms
ms
ms
ms
s
V/ms
ms
%
Notes
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 0.
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 1.
SLIMO Mode = 0.
Refer to the AC Digital Block
Specifications below.
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on timing this.
A multiple (x732) of crystal
frequency.
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the T_OSACC period. Correct
operation assumes a
properly loaded 1 W
maximum drive level 32.768
kHz crystal. -40°C  T_A 
85°C.
Vdd slew rate during power
up.
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Notes
5. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
6. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
7. See the individual user module data sheets for information on maximum frequencies for user modules.
8. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-49263 Rev. *J
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