CY8CLED16P01 Datasheet, PDF (20/58 Pages) Cypress Semiconductor – Powerline Communication Solution Integrated Powerline Modem PHY

CY8CLED16P01
8.3 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8CLED16P01-OCD On-Chip Debug PLC device. Note that the OCD parts are only used for
in-circuit debugging. OCD parts are not available for production.
Table 8-3. 100-Pin OCD Part Pinout (TQFP)
Pin
Name
No.
Description
Pin
No.
Name
Description
1
NC
No Connection
51
NC
No Connection
2
NC
No Connection
52 I/O
P5[0]
3 I/O I P0[1]
Analog Column Mux Input
53 I/O
P5[2]
4O
TX_SHUTD Output to disable transmit circuitry in receive 54 I/O
OWN
mode
Logic ‘0’ - When the Modem is transmitting
Logic ‘1’ - When the Modem is not transmitting
P5[4]
5 I/O
P2[5]
55 I/O
P5[6]
6 I/O I P2[3]
Direct switched capacitor block input
56 I/O
P3[0]
7 I/O I P2[1]
Direct switched capacitor block input
57 I/O
P3[2]
8 I/O
P4[7]
58 I/O
P3[4]
9 I/O
P4[5]
59 I/O
P3[6]
10 I/O
P4[3]
60
HCLK
OCD high speed clock output
11 I/O
P4[1]
61
CCLK
OCD CPU clock output
12
OCDE
OCD even data I/O
62
Input XRES
Active high pin reset with internal pull down
13
OCDO
OCD odd data output
63 I/O
P4[0]
14 Reserved RSVD
Reserved
64 I/O
P4[2]
15
Power Vss
Ground Connection
65
Power Vss
Ground Connection
16 I/O
P3[7]
66 I/O
P4[4]
17 I/O
P3[5]
67 I/O
P4[6]
18 I/O
P3[3]
68
O RXCOMP_OUT Analog Output to external Low Pass Filter
Circuitry
19 I/O
P3[1]
69
I RXCOMP_IN Analog Input from external Low Pass Filter
Circuitry
20 I/O
P5[7]
70
Ground AGND
Analog Ground. Connect a 1.0 µF capacitor
between the pin and Vss.
21 I/O
P5[5]
71
NC
No Connection
22 I/O
P5[3]
72 I/O
P2[6]
External Voltage Reference (VREF) input
23 I/O
P5[1]
73
NC
No Connection
24 I/O
P1[7]
I2C Serial Clock (SCL)
74 Reserved RSVD
Reserved
25
NC
No Connection
75
NC
No Connection
26
NC
No Connection
76
NC
No Connection
27
NC
No Connection
77 I/O I/O P0[2]
Analog column mux input and column
output
28 I/O
P1[5]
I2C Serial Data (SDA)
78
NC
No Connection
29 I/O
30 I/O
P1[3]
P1[1]
XTAL_STABILITY. Connect a 0.1 uF capacitor 79
between the pin and VSS.
Crystal (XTALin)^[2], I2C Serial Clock (SCL),
80
TC SCLK
I/O I/O P0[4]
NC
Analog column mux input and column output,
VREF
No Connection
31
NC
No Connection
81
I FSK_IN
Analog FSK Input
32
Power Vdd
Supply Voltage
82
Power Vdd
Supply Voltage
33
NC
No Connection
83
Power Vdd
Supply Voltage
34
Power Vss
Ground Connection
84
Power Vss
Ground Connection
35
NC
No Connection
85
Power Vss
Ground Connection
36 I/O
P7[7]
86 I/O
P6[0]
37 I/O
P7[6]
87 I/O
P6[1]
38 I/O
P7[5]
88 I/O
P6[2]
39 I/O
P7[4]
89 I/O
P6[3]
40 I/O
P7[3]
90 I/O
P6[4]
41 I/O
P7[2]
91 I/O
P6[5]
42 I/O
P7[1]
92 I/O
P6[6]
43 I/O
44 I/O
P7[0]
P1[0]
93 I/O
Crystal (XTALout)^[2], I2C Serial Data (SDA), 94
TC SDATA
P6[7]
NC
No Connection
45 I/O
46 I/O
P1[2]
P1[4]
Optional External Clock Input (EXTCLK)^[2]
95 I/O I P0[7]
96
NC
Analog Column Mux Input
No Connection
47 I/O
P1[6]
97 Reserved RSVD
Reserved
48
NC
No Connection
98
NC
No Connection
49
NC
No Connection
99
O FSK_OUT
Analog FSK Output
50
NC
No Connection
100
NC
No Connection
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test, TC/TM: Test, RSVD = Reserved (should be left unconnected).
Document Number: 001-49263 Rev. *J
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