CY7C9536B Datasheet, PDF (32/46 Pages) Cypress Semiconductor – OC-48/STM-16 Framer with VC - POSIC2GVC™

CONFIDENTIAL
CY7C9536B
Reset Requirements
Asserting the RST_n signal will asynchronously reset all
sequential elements of POSIC2GVC. Even though the reset is
treated as asynchronous signal, it is recommended that a
minimum of 1-ms-wide active LOW RST_n is applied after all
power supplies have stabilized.
Power-Up Requirements
When HSTL I/O is used, V_CC1, V_CC2, and V_CC3 need to be
powered up first before V_CC5 supply. V_CC5 shall be powered
up at least 300ms after the last of the other power supplies.
Table 6. POSIC2GVC Pin Timing Requirements
There is no particular power-up sequence requirements
among V_CC1, V_CC2, and V_CC3 in this case.
There is no particular power-up sequence requirements
among V_CC1, V_CC2, V_CC3, and V_CC5 if HSTL I/O is not used.
RST_n needs to be activated until all the power supplies have
stabilized.
AC and Timing Specifications
The POSIC2GVC device interfaces to industry standard
peripheral devices or buses. Hence the POSIC2GVC pin
timing parameters are governed by the interface requirements
of the peripherals or the relevant standards. Table 6 details the
timing requirements.
POSIC2GVC
Pin Group
Peripheral Device/Bus Standard
Line Interface
16-/8-bit HSTL/single-ended LVPECL
interface
Overhead Bytes LVTTL
Access – Serial Ports
Memory Interface LVTTL
System Interface
Host CPU Interface
UTOPIA Level 3/
OIF-SPI Level3
HBST
16-/32-bit CPU Interface LVTTL
Compatible/Suggested
Part Number
CYS25G0101DX
CY7C1370B/C or
CY7C1464V33
(min. 200-MHz grade)
Compatible with
Intel/Motorola CPUs
Reference/Remarks
Refer PHY data sheet
Described in this document
Compatible to NoBL™ or equivalent
memory chip
ATM Forum: BTD-PHY-UL3-01.05
Saturn Group: PMC-980495 Issue
Described in this document
AC Specifications
Table 7. Line Interface Timing Parameter Values
Parameter
Description
f_TS[21]
TXCLKOUT, TXCLKI Frequency (must be frequency coherent to
RXCLK when used as the transmit PLL clock source).
f_TS nominal (f_TSN) can be 155.52 MHz, 77.76 MHz, 38.88 MHz, 19.44
MHz; depends on the Bus Width and Line Rate used.
t_TXCLKIP[21]
TXCLKI Period
t_TXCLKID
t_TXCLKP[21]
t_TXCLKD[21]
t_TXCLKR[22]
t_TXCLKF[22]
TXCLKI Duty Cycle
TXCLKOUT Period
TXCLKOUT Duty Cycle
TXCLKOUT Rise Time
TXCLKOUT Fall Time
t_TXDO
TXD Output Delay after ↑ of TXCLKOUT
t_TXFPO
TXFRAME_PULSE Output Delay after ↑ of TXCLKOUT
t_PAROUTO
SONETTX_PAROUT Output Delay after ↑ of TXCLKOUT
t_TXFPPW
f_RS[21]
TXFRAME_PULSE Width
RXCLK Frequency
f_RS nominal (f_RSN) can be 155.52 MHz, 77.76 MHz, 38.88 MHz,
19.44 MHz; depends on the Bus Width and Line Rate used.
t_RXCLKP[21]
t_RXCLKOD[21]
t_RXCLKR[22]
RXCLK Period
RXCLK Duty Cycle
RXCLK Rise Time
Notes:
21. The parameter is guaranteed by design and is not tested during production.
22. The parameter is guaranteed by characterization and is not tested during production.
Min.
f_TSN *
(1 – 0.65%)
1/(f_TS max.)
43
1/(f_TS max.)
40
0.3
0.3
0.5
0.5
0.5
6
f_RSN *
(1 – 0.65%)
1/(f_RS max.)
43
–
Max.
f_TSN *
(1 + 0.65%)
1/(f_TS min.)
57
1/(f_TS min.)
60
1.5
1.5
4.5
4.5
4.5
55
f_RSN *
(1 + 0.65%)
1/(f_RS min.)
57
1.5
Unit
MHz
ns
%
ns
%
ns
ns
ns
ns
ns
ns
MHz
ns
%
ns
Document #: 38-02078 Rev. *G
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