|
CY7C9536B Datasheet, PDF (1/46 Pages) Cypress Semiconductor – OC-48/STM-16 Framer with VC - POSIC2GVC™ | |||
|
CONFIDENTIAL
CY7C9536B
OC-48/STM-16 Framer with VC - POSIC2GVCâ¢
Features
⢠OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,
OC-3/STS3/STM-1 rates, concatenated and non-concat-
enated
⢠Complies with ITU-Standards G.707/Y.1322 and
G.783[1,2]
⢠Complies with Bellcore GR253 rev.1, 1997[3]
⢠Channelized operation: supports 16xOC-3 and 4xOC-12
within OC-48 stream
⢠Supports TUG3 mapping in SDH mode
⢠Virtual concatenation enables secure and dedicated
bandwidth provisioning[4]
⢠Up to 16 channels
⢠From 50-Mbps to 1.2-Gbps bandwidth per channel
⢠STS-1 and STS-3c granularity
⢠Full duplex mapping of ATM cells over SONET/SDH
⢠Complies with ITU-Standards I 432.2[5,6,7]
⢠Full duplex mapping of packet-over-SONET/SDH: IETF
RFC 1619/1662/2615 (HDLC/PPP)[8,9,10]
⢠Generic Framing Procedure (GFP) per ANSI
T1X1.5[11,12,13] Protocol Encapsulator/Decapsulator
delineates GFP frames with length-CRC frame
construct
⢠GFP 268r1
⢠User-programmable encapsulation
⢠User-programmable clear channel transport
⢠User-programmable SONET/SDH bypass
⢠Programmable frame tagging engine for packet
preclassification enables such features as
⢠MPLS label lookup and tagging
⢠PPP: LCP and NCP tagging
⢠PPP control packets optionally sent to host CPU
interface
⢠MAC/layer 3 address look up and tagging.
⢠Programmable A1A2 processing bypass in Rx direction
with frame sync input
⢠Complete section overhead (SOH), line overhead
(LOH), and path overhead (POH) processing
⢠APS extraction, CPU interrupt generation, and
programmable insertion of APS byte
⢠Line side APS port interface
⢠Provision for protection switching on SONET/SDH port
⢠Programmable PRBS generator and receiver
⢠Serial port to access line/section data communication
channel (DCC) and voice communication channel
(VCC)
⢠Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3
interface[14,15]
⢠16-bit/32-bit host CPU interface bus
⢠JTAG and boundary scan
⢠Glueless interface with Cypress CYS25G0101DX
OC-48 PHY
⢠0.18-um CMOS, 504-pin BGA package
⢠+1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for
HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
Applications
⢠Multi-service nodes
⢠ATM switches and routers
⢠Packet routers and multiservice routers
⢠SONET/SDH/Add-Drop Mux for packet/data applications
⢠SONET/SDH/ATM/POS test equipment
Notes:
1. ITU-T Recommendation G.707. âNetwork Node Interface for the Synchronous Digital Hierarchy.â 1996.
2. ITU-T Recommendation G.783. âCharacteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.â 2000.
3. Bellcore Publication GR-253-Core. âSynchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.â 1997.
4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. âExtending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order
payloads.â Internet Draft. June 2000.
5. ITU-T Recommendation I.432.3. âB-ISDN User-Network InterfaceâPhysical Layer Specification: 1544 kbit/s and 2048 kbit/s Operation.â 1999.
6. American National Standards Institute. âSynchronous Optical Network (SONET)âBasic Description Including Multiplex Structure, Rates and Formats.â ANSI
T1.105-1995.
7. American National Standards Institute. âSynchronous Optical Network (SONET)âPayload Mappings.â ANSI T1.105.02â1998.
8. Simpson, W. âPPP over SONET/SDH.â RFC 1619. May 1994.
9. Simpson, W., ed. âPPP in HDLC-like Framing,â RFC 1662. Daydreamer. July 1994.
10. Malis, A. and W. Simpson. âPPP over SONET/SDH,â RFC 2615. June 1999.
11. Hernandez-Valencia, E., Lucent Technologies. âA Generic Frame Format for Data over SONET (DoS).â March 2000.
12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.
13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. âGeneric Framing Procedure (GFP) Specification.â October 9â13, 2000.
14. ATM Forum, Technical Committee. UUTOPIA 3 Physical Layer Interface.â Af-phy-0136.000. November 1999.
15. Can, R. and R. Tuck. âSystem Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices.â OIF-SPI3-01.0. June 2000.
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Document #: 38-02078 Rev. *G
Revised April 25, 2005
|
▷ |