CY7C9536B Datasheet, PDF (3/46 Pages) Cypress Semiconductor – OC-48/STM-16 Framer with VC - POSIC2GVC™

CONFIDENTIAL
CY7C9536B
Overview
The CY7C9536B (POSIC2GVC) is a highly integrated
SONET/SDH framer device for transport of ATM and IP
packets over SONET/SDH links. It features special functions
and architecture to support next-generation optical networking
protocols for both SONET/SDH and direct data-over-fiber
networks. OIF-SPI (POS-PHY) level 3, UTOPIA level 3 and
High-Bandwidth Synchronous Transfer (HBST) interfaces are
provided on the system side.
POSIC2GVC performs complete SOH, LOH, and POH
processing. Complete access to all overhead bytes is provided
through register access via the host CPU interface. Access to
selected overhead bytes are also available through serial port.
Optional frame sync input and Transport Overhead (TOH)
bypass enables better interface with STS-1 switched streams.
The virtual concatenation feature, with up to 16 channels,
enables provisioning of secure, dedicated and right-sized
bandwidth for Ethernet or ATM transport. Up to 16 virtual
channels can be created with STS-1 or STS-3c granularity.
Bandwidth from 50 Mbps to 1.2 Gbps can be allocated per
channel.
POSIC2GVC supports packet over SONET/SDH as PPP in
HDLC-like frame as per IETF rfc 1619/1662/2615 (PPP).
POSIC2GVC also supports full duplex ATM over SONET/SDH
transport in compliance with ITU I432.2.
POSIC2GVC supports the new generation Generic Framing
Procedure (GFP) protocol encapsulation/Decapsulation over
SONET/SDH. This protocol engine features wire rate framing,
frame delineation and deframing with length-CRC pair header
construct. Optional payload scrambling/descrambling and
payload FCS are also provided.
Clear channel mode enables transport of any raw byte
streams on selected virtual channels, while the rest of the
channels are transporting data through any one of encapsu-
lation/decapsulation engines.
The Programmable Frame Tagging Engine enables wire rate
tagging of packets/frames. For new generation networking
features such as MPLS, this engine can be programmed to tag
based on existence/lack of specific label/field values, in the
first 64 bytes of each packet. This way, packets are tagged for
a variety of conditions, all programmable by the user, enabling
sorting of packets in the incoming data stream and buffering
packets accordingly. In a PPP application, control packets can
optionally be sent over the host CPU interface directly.
SONET/SDH bypass mode allows use of this device for data
transport in non SONET/SDH point-to-point and mesh optical
networks.
Transmit
In the transmit direction, packets are received from the system
side, encapsulated/framed and mapped into the SONET/SDH
payload. Finally the TOH is added and SONET/SDH frames
are passed onto the fiber side/line side interface on a parallel
bus.
The system side interface can be programmed either as
OIF-SPI level 3, or UTOPIA level 3 or HBST modes. In the
UTOPIA mode, ATM cells can be received either in 54- (8-bit
interface) or 56- (8-bit and 32-bit interfaces) bytes format. The
sixth byte carries the channel number of the cell. In case of
packets, the interface can be programmed as OIF-SPI level 3
or HBST operations. In these cases, the first data transfer
always carry the channel number.
POSIC2GVC supports three basic types of encapsulation,
namely (i) ATM, (ii) HDLC frame, and (iii) GFP (frames with
length-CRC pair header construct based delineation). Clear
channel or transparent mode (no encapsulation) is also
supported. While in operation, only one type of encapsulation
can be enabled for all VC channels. Some or all of the VC
channels can be programmed as clear channels. For Clear
Channels, the encapsulator engine will bypass the encapsu-
lation and pass the packets without any processing to the next
block.
Encapsulated packets are transferred to the Virtual Concate-
nation (VC) block along with the channel number. The VC
block rearranges the packet/frame flow to support the
bandwidth allocation for virtual channels. Bandwidth is
assigned by allocating a programmed number of SPEs to each
channel. The VC block keeps track of the SPE under
construction by the SONET/SDH framer block and transfers
the packets meant for a given channel to the SONET framer.
Since POSIC2GVC does not have a packet storage memory
on-chip, a channel bandwidth balanced packet flow is
expected from the system side. To enable such a balanced
transfer, POSIC2GVC has internal FIFO of 512 bytes per
channel. The status of FIFO is provided through pins to the link
layer.
Finally, the SONET/SDH framer inserts the packet /cells into
the SONET/SDH frame. All overhead bytes are added. All
alarm bits and status bits are inserted based on the status of
incoming frames as well as programming done by the host
CPU. The scrambler meets relevant standards and can
optionally be disabled. Frames are finally sent out on the fiber
side interface. If programmed to do so, the SONET/SDH
framer can be bypassed and encapsulated packets/frames
can be sent directly to the fiber-side interface.
Receive
In the receive direction, SONET/SDH frames are received
from the fiber side. Data packets/frames are extracted from the
payload and passed onto the selected decapsulator engine
after compensation for differential delay, in case of virtual
concatenation. If the SONET/SDH framer is bypassed, the
incoming data stream is directly passed over to the decapsu-
lator engine. Data packets/frames are then decapsulated and
sent to the Programmable Frame Tagging Engine. They are
then analyzed and tagged before sent out to the system side
via the OIF-SPI level 3, UTOPIA or HBST interface. Tagging
of frames is optional.
SONET/SDH frames entering from the fiber side are synchro-
nized and the frame boundary is identified with A1A2 bytes.
Frames can be optionally synchronized with
Frame_Sync_Input to identify the boundary. Descrambling is
performed to retrieve scrambled frames. Complete processing
of all overhead bytes, Section, Line and Path, is performed
and all alarm bits are verified and alarms are raised as
programmed. Full access to all overhead bytes is provided
through register access. Access to selected overhead bytes is
also provided through serial bus. The SONET/SDH deframing
can be entirely bypassed.
The extracted payload is transferred to the VC block where it
is reorganized to compensate for any differential delay
encountered in the network from the virtual concatenation
Document #: 38-02078 Rev. *G
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