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| CY7C43646AV Datasheet, PDF (31/40 Pages) Cypress Semiconductor – 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO | |||
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Switching Waveforms (continued)
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)[48]
CLKB
tCLK
tCLKH tCLKL
CSB
MBB
RENB
LOW
LOW
tENS tENH
EFB/ORB
B0â17
CLKA
FFA/IRA
HIGH
tA
Previous Word in FIFO1 Next Word From FIFO1
Output Register tSKEW1[50] tCLKH tCLKL
FIFO1 Full
tCLK
tWFF
tWFF
CSA
LOW
W/RA
MBA
ENA
A0â35
HIGH
tEN tENH
tEN tENH
tDS tDH
Read Disabled
Note:
50. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06026 Rev. *C
Page 31 of 40
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