CY7C43646AV Datasheet, PDF (29/40 Pages) Cypress Semiconductor – 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO

Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)^[46]
t_CLK
t_CLKH t_CLKL
CLKC
MBC
WENC
t_ENSt_ENH
t_ENSt_ENH
FFC/IRC HIGH
t_DS t_DH
C_0–17
CLKA
EFA/ORA
W1
t_SKEW1^{[47] tCLKH}
t_CLKL
t_CLK
FIFO2 Empty
t_REF
t_REF
CSA
LOW
W/RA
LOW
MBA
ENA
A_0–35
LOW
t_EN t_ENH
t_A
CY7C43646AV
CY7C43666AV
CY7C43686AV
W1
Notes:
46. If Port C size is word or byte, t_SKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
47. t_SKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKC edge and rising CLKA edge is less than t_SKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Document #: 38-06026 Rev. *C
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