CY7C43646AV Datasheet, PDF (1/40 Pages) Cypress Semiconductor – 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO

3686AV
CY7C43646AV
CY7C43666AV
CY7C43686AV
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO
Features
• 3.3V high-speed, low-power, First-In First-Out (FIFO)
memories with three independent ports (one bidirec-
tional ×36, and two unidirectional ×18)
• 1K ×36/×18×2 (CY7C43646AV)
• 4K ×36/×18×2 (CY7C43666AV)
• 16K ×36/×18×2 (CY7C43686AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
— I_CC= 60 mA
— I_SB= 10 mA
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and serial programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user-selectable mode
• Partial and master reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A_0–35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail1
Reset
Logic
MBF2
Mail1
Register
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO1)
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Read
Pointer
1
Pointer
1K/4K/16K
× 36
Dual Ported
Memory
(FIFO2)
Mail2
Register
MBF1
Port B
Control
Logic
B_0–17
CLKB
RENB
CSB
SIZEB
MBB
RTI
Common
Port Logic
(B and C)
FIFO2,
Mail2
Reset
Logic
Port C
Control
Logic
EFB/ORB
AEB
BE/FWFT
FFC/IRC
AFC
MRS2
PRS2
C_0–17
CLKC
WENC
SIZEC
MBC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06026 Rev. *C
Revised December 26, 2002