CYP15G0101DXA Datasheet, PDF (29/40 Pages) Cypress Semiconductor – Single Channel HOTLink II Transceiver

PRELIMINARY
CYP15G0101DXA
CYP15G0101DXA HOTLink II Transmitter Switching Waveforms (continued)
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = LOW
REFCLK
Note 34
t_REFCLK
t_REFH
Note 33
t_REFL
t_TXCLKO
t_TXCLKOD+
t_{TXCLKOD–}
TXCLKO
Switching Waveforms for the CYP15G0101DXA HOTLink II Receiver
Receive Interface
Read Timing
RXCKSEL = LOW
RXRATE = LOW
REFCLK
RXD[7:0],
RXST[2:0],
RXOP
RXCLK
RXCLKC
t_REFH
t_REFCLK
t_REFL
t_RREFDA
t_RREFDV
t_REFADV+
t_REFCDV+
Note 35
t_REFADV–
t_REFCDV–
Receive Interface
Read Timing
RXCKSEL = LOW
TXRATE = HIGH
REFCLK
RXD[7:0],
RXST[2:0],
RXOP
RXCLK
RXCLKC
t_REFH
t_RREFDA
t_RREFDV
t_REFCLK
t_REFL
t_RREFDV
t_RREFDA
t_REFADV+
t_REFCDV+
Note 35
t_REFADV–
t_REFCDV–
Note 36
Note:
35. RXCLK and RXCLKC are a delayed in phase from REFCLK, and are different in phase from each other.
36. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLK and RXCLKC are relative to both rising and falling
edges of the clock output
Document #: 38-02061 Rev. **
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