CYP15G0101DXA Datasheet, PDF (15/40 Pages) Cypress Semiconductor – Single Channel HOTLink II Transceiver

PRELIMINARY
CYP15G0101DXA
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the Transmit Shifter. It also
provides a character-rate clock used by the transmit path.
This clock multiplier PLL can accept a REFCLK input between
20 MHz and 150 MHz, however, this clock range is limited by
the operating mode of the CYP15G0101DXA clock multiplier
(controlled by TXRATE) and by the level on the SPDSEL input.
SPDSEL is a 3-level select^[2] (ternary) input that selects one
of three operating ranges for the serial data outputs and inputs.
The operating serial signaling-rate and allowable range of
REFCLK frequencies are listed in Table 9.
Table 9. Operating Speed Settings
SPDSEL
LOW
MID (Open)
HIGH
TXRATE
1
0
1
0
1
0
REFCLK
Frequency
(MHz)
reserved
20–40
20–40
40–80
40–75
80–150
Signaling
Rate
(MBaud)
200–400
400–800
800–1500
The REFCLK± input is a differential input with each input inter-
nally biased to 1.4V. If the REFCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, the input signal is rec-
ognized when it passes through the internally biased reference
point.
When both the REFCLK+ and REFCLK− inputs are connect-
ed, the clock source must be a differential clock. This can be
either a differential LVPECL clock that is DC-or AC-coupled,
or a differential LVTTL or LVCMOS clock.
By connecting the REFCLK− input to an external voltage
source or resistive voltage divider, it is possible to adjust the
reference point of the REFCLK+ input for alternate logic levels.
When doing so it is necessary to ensure that the 0V-differential
crossing point remains within the parametric range supported
by the input.
CYP15G0101DXA Receive Data Path
Serial Line Receivers
Two differential Line Receivers, IN1± and IN2±, are available
for accepting serial data streams. The active Serial Line Re-
ceiver is selected using the INSEL input. Both Serial Line Re-
ceivers have differential inputs, and can accommodate wire
interconnect and filtering losses or transmission line attenua-
tion greater than 16 dB. For normal operation, these inputs
should receive a signal of at least VI_DIFF > 100 mV, or 200 mV
peak-to-peak differential. Each Line Receiver can be DC- or
AC-coupled to +3.3V powered fiber-optic interface modules
(any ECL/PECL logic family, not limited to 100K PECL) or AC-
coupled to +5V powered optical modules. The common-mode
tolerance of accommodates a wide range of signal termination
voltages. Each receiver provides internal DC-restoration, to
the center of the receiver’s common mode range, for AC-cou-
pled signals.
The local loopback input (LPEN) allows the serial transmit data
to be routed internally back to the Clock and Data Recovery
circuit. When configured for local loopback, the transmit Serial
Driver outputs are forced to output a differential logic-1. This
prevents local diagnostic patterns from being broadcast to at-
tached remote receivers.
Signal Detect / Link Fault
Each selected Line Receiver (i.e., that routed to the Clock and
Data Recovery PLL) is simultaneously monitored for
• analog amplitude
• transition density
• Range Control logic report the received data stream inside
normal frequency range (±200 ppm)
• receive channel enabled.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI (Link Fault Indicator) output which changes synchro-
nous to the selected receive interface clock.
Table 10. Analog Amplitude Detect Valid Signal Levels
SDASEL
LOW
MID (Open)
HIGH
Typical signal with peak amplitudes above
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow opera-
tion with highly attenuated signals, or in high-noise environ-
ments. This adjustment is made through the SDASEL signal,
a 3-level select^[2] (ternary) input, which sets the trip point for
the detection of a valid signal at one of three levels, as listed
in Table 10.
The Analog Signal Detect monitor is active for the present Line
Receiver, as selected by the INSEL input. When configured for
local loopback (LPEN = HIGH), no Line Receiver is selected,
and the LFI output reports only the receive VCO frequency out-
of-range and transition density status. When local loopback is
active, the Analog Signal Detect monitor is disabled.
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received (with-
in the referenced period), the Transition Detection logic as-
serts LFI. The LFI output remains asserted until at least one
transition is detected in each of three adjacent received char-
acters.
Range Control
The receive-VCO Range-Control Monitor tracks the frequency
of the received signal relative to REFCLK. It also determines
if the receive Clock/Data Recovery circuit (CDR) should align
the receive-VCO clock to the data stream or to the local
REFCLK input. This prevents the receive VCO from tracking
an out-of-specification received signal.
When the Range-Control Monitor indicates that the signaling
rate is within specification, the phase detector in the receive
PLL is configured to track the transitions in the received data
Document #: 38-02061 Rev. **
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