CYP15G0101DXA Datasheet, PDF (11/40 Pages) Cypress Semiconductor – Single Channel HOTLink II Transceiver

PRELIMINARY
CYP15G0101DXA
CYP15G0101DXA HOTLink II Operation
The CYP15G0101DXA is a highly configurable device de-
signed to support reliable transfer of large quantities of data,
using a high-speed serial links, from a single source to one or
more destinations.
CYP15G0101DXA Transmit Data Path
Operating Modes
The transmit path of the CYP15G0101DXA supports a single-
character-wide data path. This data path is used in multiple
operating modes as controlled by the TXMODE[1:0] inputs.
Input Register
Within these operating modes, the bits in the Input Register
support different bit assignments, based on if the character is
unencoded, encoded with two control bits, or encoded with
three control bits. These assignments are shown in Table 1.
Table 1. Input Register Bit Assignments^[3]
Signal Name
Unencoded
(Encoder
Bypassed)
Encoded
(Encoder Enabled)
2-bit
Control
3-bit
Control
TXD[0] (LSB)
DIN[0]
TXD[0]
TXD[0]
TXD[1]
DIN[1]
TXD[1]
TXD[1]
TXD[2]
DIN[2]
TXD[2]
TXD[2]
TXD[3]
DIN[3]
TXD[3]
TXD[3]
TXD[4]
DIN[4]
TXD[4]
TXD[4]
TXD5]
DIN[5]
TXD[5]
TXD[5]
TXD[6]
DIN[6]
TXD[6]
TXD[6]
TXD[7]
DIN[7]
TXD[7]
TXD[7]
TXCT[0]
DIN[8]
TXCT[0] TXCT[0]
TXCT[1] (MSB)
DIN[9]
TXCT[1] TXCT[1]
SCSEL
N/A
N/A
SCSEL
Note:
3. The TXOP input is also captured in the Input Register, but its interpreta-
tion is under the separate control of PARCTL.
The Input Register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the Encoder
is bypassed, the control bits are part of the pre-encoded 10-bit
data character.
When the Encoder is enabled (TXMODE[1] ≠ LOW), the
TXCT[1:0] bits are interpreted along with the TXD[7:0] charac-
ter to generate the specific 10-bit transmission character.
When TXMODE[0] ≠ HIGH, an additional special character
select (SCSEL) input is also captured and interpreted. This
SCSEL input is used to modify the encoding of the characters.
Phase-Align Buffer
Data from the Input Register is passed either to the Encoder
or to the Phase-Align buffer. When the transmit path is operat-
ed synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the Phase-Align Buffer is bypassed and
data is passed directly to the Parity Check and Encoder block
to reduce latency.
When an Input-Register clock with an uncontrolled phase re-
lationship to REFCLK is selected (TXCKSEL ≠ LOW) or if data
is captured on both edges of REFCLK (TXRATE = HIGH), the
Phase-Align Buffer is enabled. This buffer is used to absorb
clock phase differences between the presently selected input
clock and the internal character clock.
Initialization of the Phase-Align Buffer takes place when the
TXRST input is sampled LOW by TXCLK↑. When TXRST is
returned HIGH, the present input clock phase relative to
REFCLK↑ is set. TXRST is an asynchronous input, but is sam-
pled internally to synchronize it to the internal transmit path
state machine. TXRST must be sampled LOW by a minimum
of two consecutive TXCLK↑ clocks to ensure the reset opera-
tion is initiated correctly.
Once set, the input clock is allowed to skew in time up to half
a character period in either direction relative to REFCLK↑; i.e.,
±180°. This time shift allows the delay path of the character
clock (relative to REFLCK↑) to change due to operating volt-
age and temperature, while not affecting the design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the TXPER
output. This output indicates a continuous error until the
Phase-Align Buffer is reset. While the error remains active, the
transmitter will output a continuous C0.7 character to indicate
to the remote receiver that an error condition is present in the
link.
In specific transmit modes it is also possible to reset the
Phase-Align Buffer and with minimal disruption of the serial
data stream. When the transmit interface is configured for gen-
eration of atomic Word Sync Sequences (TXMODE[1] = MID)
and a Phase-Align Buffer error is present, the transmission of
a Word Sync Sequence will re-center the Phase-Align Buffer
and clear the error condition.
NOTE: One or more K28.5 characters may be added or lost
from the data stream during this reset operation. When
used with non-Cypress devices that require a complete 16-
character Word Sync Sequence for proper receive Elastic-
ity Buffer alignment, it is recommend that the sequence be
followed by a second Word Sync Sequence to ensure prop-
er operation.
Parity Support
In addition to the ten data and control bits that are captured at
the transmit Input Register, a TXOP input is also available.
This allows the CYP15G0101DXA to support ODD parity
checking. Parity checking is available for all operating modes
(including Encoder Bypass). The specific mode of parity
checking is controlled by the PARCTL input, and operates per
Table 2.
When PARCTL = MID (open) and the Encoder is enabled
(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked
for ODD parity along with the TXOP bit. When
PARCTL = HIGH with the Encoder enabled (or MID with the
Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are
checked for ODD parity along with the TXOP bit. When
PARCTL = LOW, parity checking is disabled.
When parity checking and the Encoder are both enabled
(TXMODE[1] ≠ LOW), the detection of a parity error causes a
C0.7 character of proper disparity to be passed to the Transmit
Shifter. When the Encoder is bypassed (TXMODE[1] = LOW),
Document #: 38-02061 Rev. **
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