CY7C1561V18 Datasheet, PDF (28/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
Document History Page
Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Archi-
tecture (2.5 Cycle Read Latency)
Document Number: 001-05384
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
** 402911 See ECN VEE New Data Sheet
*A 425251 See ECN VEE Updated the switching waveform
Corrected the typos in DC parameters
Updated the DLL section
Added additional notes in the AC parameter section
Updated the Power up sequence
Added additional parameters in the AC timing
*B 437000 See ECN IGS ECN for Show on web
*C 461934 See ECN NXR Moved the Selection Guide table from page# 3 to page# 1.
Modified Application Diagram.
Changed t_TH and t_TL from 40 ns to 20 ns, changed t_TMSS, t_TDIS, t_CS, t_TMSH, t_TDIH, t_CH
from 10 ns to 5 ns and changed t_TDOV from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified Power Up waveform.
Included Maximum ratings for Supply Voltage on V_DDQ Relative to GND.
Changed the Maximum Ratings for DC Input Voltage from V_DDQ to V_DD.
Changed the Pin Definition of I_X from Input Load current to Input Leakage current on
page#18.
*D 497567 See ECN NXR Changed the V_DDQ operating voltage to 1.4V to V_DD in the Features section, in
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C
to +85°C to –55°C to +125°C
Changed V_REF (Max) spec from 0.85V to 0.95V in the DC Electrical Characteristics
table and in the note below the table
Updated footnote #21 to specify Overshoot and Undershoot Spec
Updated I_DD and I_SB values
Updated Θ_JA and Θ_JC values
Removed x9 part and its related information
Updated footnote #25
*E 1351243 See ECN VKN/FSU Converted from preliminary to final
Added x8 and x9 parts
Changed t_CYC max spec to 8.4 ns for all speed bins
Updated footnote# 23
Updated Ordering Information table
© Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Document Number: 001-05384 Rev. *E
Revised July 24, 2007
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.