CY7C1561V18 Datasheet, PDF (11/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
Write Cycle Descriptions
The write cycle description table for CY7C1565V18 follows. ^{[3, 11]}
BWS₀ BWS₁ BWS₂ BWS₃ K
L
L
L
L L–H
K
Comments
– During the Data portion of a write sequence, all four bytes (D_[35:0]) are written into
the device.
L
L
L
L
– L–H During the Data portion of a write sequence, all four bytes (D_[35:0]) are written into
the device.
L
H
H
H L–H – During the Data portion of a write sequence, only the lower byte (D_[8:0]) is written
into the device. D_[35:9] remains unaltered.
L
H
H
H
– L–H During the Data portion of a write sequence, only the lower byte (D_[8:0]) is written
into the device. D_[35:9] remains unaltered.
H
L
H
H L–H – During the Data portion of a write sequence, only the byte (D_[17:9]) is written into
the device. D_[8:0] and D_[35:18] remains unaltered.
H
L
H
H
– L–H During the Data portion of a write sequence, only the byte (D_[17:9]) is written into
the device. D_[8:0] and D_[35:18] remains unaltered.
H
H
L
H L–H – During the Data portion of a write sequence, only the byte (D_[26:18]) is written into
the device. D_[17:0] and D_[35:27] remains unaltered.
H
H
L
H
– L–H During the Data portion of a write sequence, only the byte (D_[26:18]) is written into
the device. D_[17:0] and D_[35:27] remains unaltered.
H
H
H
L L–H – During the Data portion of a write sequence, only the byte (D_[35:27]) is written into
the device. D_[26:0] remains unaltered.
H
H
H
L
– L–H During the Data portion of a write sequence, only the byte (D_[35:27]) is written into
the device. D_[26:0] remains unaltered.
H
H
H
H L–H – No data is written into the device during this portion of a write operation.
H
H
H
H
– L–H No data is written into the device during this portion of a write operation.
Document Number: 001-05384 Rev. *E
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