CY7C1561V18 Datasheet, PDF (24/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
Switching Waveforms
Read/Write/Deselect Sequence^{[30, 31, 32]}
Figure 3. Waveform for 2.5 Cycle Read Latency
NOP
READ WRITE READ WRITE NOP
1
2
3
4
5
6
7
8
K
tKH tKL
K
tCYC
tKHKH
RPS
WPS
A
D
QVLD
Q
CQ
CQ
tSC tHC
t _SC tHC
A0
A1
A2
A3
tSA tHA
t _HD
t _SD
D10
tSD
D11 D12
t _QVLD
tCLZ ^tCO
t _HD
D13 D30 D31
tDOH
tCQD
D32 D33
tQVLD
tCQDOH
tCHZ
(Read Latency = 2.5 Cycles)
Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23
tCQOH
tCCQO
tCQH ^tCQHCQH
tCQOH
tCCQO
DON’T CARE
UNDEFINED
Notes
30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
31. Outputs are disabled (High-Z) one clock cycle after a NOP.
32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-05384 Rev. *E
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