CY7C1561V18 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 400 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both Read and Write
Ports (data transferred at 800 MHz) at 400 MHz
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for both Read and Write Ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core V_DD = 1.8V ± 0.1V; IO V_DDQ = 1.4V to V_DD[1]
■ HSTL inputs and Variable drive HSTL output buffers
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1561V18 – 8M x 8
CY7C1576V18 – 8M x 9
CY7C1563V18 – 4M x 18
CY7C1565V18 – 2M x 36
Functional Description
The CY7C1561V18, CY7C1576V18, CY7C1563V18, and
CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ SRAMs consists of two separate ports to
access the memory array. The Read Port has dedicated data
outputs to support read operations and the Write Port has
dedicated data inputs to support write operations. QDR-II+ archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common IO devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR-II+ Read and Write Ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write Ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1561V18), 9-bit words
(CY7C1576V18), 18-bit words (CY7C1563V18), or 36-bit words
(CY7C1565V18) that burst sequentially into or out of the device.
Since data can be transferred into and out of the device on every
rising edge of both input clocks (K and K), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with port selects for each port.
Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
x8
1400
x9
1400
x18
1400
x36
1400
375 MHz
375
1300
1300
1300
1300
333 MHz
333
1200
1200
1200
1200
300 MHz
300
1100
1100
1100
1100
Unit
MHz
mA
Note
1. The QDR consortium specification for V_DDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V_DDQ = 1.4V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-05384 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 24, 2007