CYF0018V_13 Datasheet, PDF (25/36 Pages) Cypress Semiconductor – 18/36/72-Mbit Programmable FIFOs

Switching Waveforms (continued)
Figure 19. Full Flag Deassertion
CYF0018V
CYF0036V
CYF0072V
WCLK
WEN / IE
D_[35:0]
D
LAST-5
D
LAST-4
D
LAST-3
D
LAST-2
D
LAST-1
D
LAST
FF
RCLK
REN
0
1
2
3
8
L _{FF_DEASSERT}
Figure 20. PAE Assertion and Deassertion
WCLK
WEN / IE
Note 6
RCLK
REN
PAE
L _{WEN_TO_PAE_HI}
1 READ
tPAE
L _{REN_TO_PAE_LO}
tPAE
Note
6. Refer to Table 2 on page 8 and Latency Table on page 16 for the Programmable Flag boundaries.
Document Number: 001-53687 Rev. *M
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