CYF0018V_13 Datasheet, PDF (18/36 Pages) Cypress Semiconductor – 18/36/72-Mbit Programmable FIFOs

Switching Characteristics
Parameter
Description
t_PU
t_S
t_S
t_A
t_CLK
t_CLKH
t_CLKL
t_DS
t_DH
t_ENS
t_ENH
t_{ENS_SI}
t_{ENH_SI}
t_{RATE_SPI}
t_RS
t_PZS
t_PZH
t_RSF
t_PRT
Power-up time after all supplies reach minimum value
Clock cycle frequency
3.3 V LVCMOS
Clock cycle frequency
1.8 V LVCMOS
Data access time
Clock cycle time
Clock high time
Clock low time
Data setup time
Data hold time
Enable setup time
Enable hold time
Setup time for SPI_SI and SPI_SEN pins
Hold time for SPI_SI and SPI_SEN pins
Frequency of SCLK
Reset pulse width
Port size select to MRS seup time
MRS to port size select hold time
Reset to flag output time
Retransmit pulse width
t_OLZ
t_OE
t_OHZ
t_WFF
t_REF
t_PAF
t_PAE
t_HF
t_PLL
t_{RATE_JTAG}
t_{S_JTAG}
t_{H_JTAG}
t_{CO_JTAG}
Output enable to output in Low Z
Output enable to output valid
Output enable to output in High Z
Write clock to FF
Read clock to EF
Clock to PAF flag
Clock to PAE flag
Clock to HF flag
Time required to synchronize PLL
JTAG TCK cycle time
Setup time for JTAG TMS,TDI
Hold time for JTAG TMS,TDI
JTAG TCK low to TDO valid
CYF0018V
CYF0036V
CYF0072V
-133
Min
Max
–
2
24
133
24
133
–
10
7.5
41.67
3.375
–
3.375
–
3
–
3
–
3
–
3
–
5
–
5
–
–
25
100
–
25
–
25
–
–
50
5
–
4
15
–
15
–
15
–
8.5
–
8.5
–
17
–
17
–
17
–
1024
100
–
8
–
8
–
–
20
Unit
ms
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
RCLK
cycles
ns
ns
ns
ns
ns
ns
ns
ns
cycles
ns
ns
ns
ns
Document Number: 001-53687 Rev. *M
Page 18 of 36