CYF0018V_13 Datasheet, PDF (1/36 Pages) Cypress Semiconductor – 18/36/72-Mbit Programmable FIFOs

CYF0018V
CYF0036V
CYF0072V
18/36/72-Mbit Programmable FIFOs
18/36/72-Mbit Programmable FIFOs
Features
■ Memory organization
❐ Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit, and 72-Mbit
❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
■ Up to 133-MHz clock operation
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐ Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
■ Input and output enable control for write mask and read skip
operations
■ Mark and retransmit: resets read pointer to user marked
position
■ Empty, full, half-full, and programmable almost-empty and
almost-full status flags with configured offsets
■ Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
■ Configure programmable flags and registers through serial or
parallel modes
■ Separate serial clock (SCLK) input for serial programming
■ Master reset to clear entire FIFO
■ Partial reset to clear data but retain programmable settings
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The user-programmable registers
enable user to configure the device operation as desired. The
device also offers a simple and easy-to-use interface to reduce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including multiprocessor
interfaces, video and image processing, networking and
telecommunications, high-speed data acquisition, or any system
that needs buffering at high speeds across different clock
domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. If writes and inputs are
enabled (WEN & IE), data on the write port gets written into the
device at the rising edge of write clock. Enabling reads and
outputs (REN & OE) fetches data on the read port at every rising
edge of read clock. Both reads and writes can occur
simultaneously at different speeds provided the ratio between
read and write clock is in the range of 0.5 to 2. Appropriate flags
are set whenever the FIFO is empty, almost-empty, half-full,
almost-full or full.
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All product features and specs are common to all densities
(CYF0072V, CYF0036V, and CYF0018V). All descriptions are
given assuming the 72Mbit (CYF0072V) device is operated in
× 36 mode. They are valid for other densities (CYF0036V, and
CYF0018V) and all port sizes × 9, × 12, × 16, × 18, × 20, × 24
and × 32 unless otherwise specified. The only difference will be
in the input and output bus width. Table 1 on page 7 shows the
part of bus with valid data from D[35:0] and Q[35:0] in × 9, × 12,
× 16, × 18, × 20, × 24, × 32 and × 36 modes.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53687 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 11, 2013