CYBLE-212006-01 Datasheet, PDF (25/39 Pages) Cypress Semiconductor – Module size: 15.00 mm × 23.00 mm × 2.00 mm

PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Voltage Monitors (LVD)
Table 45. Voltage Monitor DC Specifications
Parameter
V_LVI1
V_LVI2
V_LVI3
V_LVI4
V_LVI5
V_LVI6
V_LVI7
V_LVI8
V_LVI9
V_LVI10
V_LVI11
V_LVI12
V_LVI13
V_LVI14
V_LVI15
V_LVI16
LVI_IDD
Description
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Block current
Table 46. Voltage Monitor AC Specifications
Parameter
Description
T_MONTRIP
Voltage monitor trip time
SWD Interface
Table 47. SWD Interface Specifications
Parameter
Description
F_SWDCLK1
3.3 V  V_DD  5.5 V
F_SWDCLK2
1.71 V  V_DD  3.3 V
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
Min
Typ Max Units
1.71 1.75 1.79
V
1.76 1.80 1.85
V
1.85 1.90 1.95
V
1.95 2.00 2.05
V
2.05 2.10 2.15
V
2.15 2.20 2.26
V
2.24 2.30 2.36
V
2.34 2.40 2.46
V
2.44 2.50 2.56
V
2.54 2.60 2.67
V
2.63 2.70 2.77
V
2.73 2.80 2.87
V
2.83 2.90 2.97
V
2.93 3.00 3.08
V
3.12 3.20 3.28
V
4.39 4.50 4.61
V
–
–
100
A
Min
Typ Max Units
–
–
1
s
Details/Conditions
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Details/Conditions
–
Min Typ
–
–
–
–
0.25 × T –
0.25 × T –
–
–
1
–
Max
14
7
–
–
0.5 × T
–
Units
MHz
MHz
ns
ns
ns
ns
Details/Conditions
SWDCLK 1/3 CPU clock frequency
SWDCLK 1/3 CPU clock frequency
–
–
–
–
Document Number: 002-15631 Rev.*B
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