CYBLE-212006-01 Datasheet, PDF (24/39 Pages) Cypress Semiconductor – Module size: 15.00 mm × 23.00 mm × 2.00 mm

PRELIMINARY
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Memory
Table 39. Flash DC Specifications
Parameter
V_PE
T_WS48
T_WS32
T_WS16
Description
Erase and program voltage
Number of Wait states at 32–48 MHz
Number of Wait states at 16–32 MHz
Number of Wait states for 0–16 MHz
Min Typ Max Units
Details/Conditions
1.71
–
5.5
V
–
2
–
–
CPU execution from flash
1
–
–
CPU execution from flash
0
–
–
CPU execution from flash
Table 40. Flash AC Specifications
Parameter
Description
Min Typ
T_ROWWRITE[12] Row (block) write time (erase and program)
–
–
T_ROWERASE[12] Row erase time
–
–
T_{ROWPROGRAM[12]} Row program time after erase
–
–
T_{BULKERASE[12]} Bulk erase time (256 KB)
–
–
T_DEVPROG[12]
Total device program time
–
–
F_END
Flash endurance
100 K –
F_RET
Flash retention. T_A  55 °C, 100 K P/E cycles 20
–
F_RET2
Flash retention. T_A  85 °C, 10 K P/E cycles
10
–
System Resources
Power-on-Reset (POR)
Table 41. POR DC Specifications
Parameter
V_RISEIPOR
V_FALLIPOR
V_IPORHYST
Description
Rising trip voltage
Falling trip voltage
Hysteresis
Min Typ
0.80
–
0.75
–
15
–
Table 42. POR AC Specifications
Parameter
T_{PPOR_TR}
Description
Precision power-on reset (PPOR) response
time in Active and Sleep modes
Min Typ
–
–
Max Units
Details/Conditions
20
ms Row (block) = 256 bytes
13
ms
–
7
ms
–
35
ms
–
25 seconds
–
– cycles
–
– years
–
– years
–
Max Units
1.45
V
1.40
V
200 mV
Details/Conditions
–
–
–
Max Units
1
s
Details/Conditions
–
Table 43. Brown-Out Detect
Parameter
Description
Min Typ Max Units
V_FALLPPOR
BOD trip voltage in Active and Sleep modes 1.64
–
–
V
V_FALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
V
Details/Conditions
–
–
Table 44. Hibernate Reset
Parameter
V_HBRTRIP
Description
BOD trip voltage in Hibernate
Min Typ Max Units
1.1
–
–
V
Details/Conditions
–
Note
12. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-15631 Rev.*B
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