CY7C455 Datasheet, PDF (2/23 Pages) Cypress Semiconductor – 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags

CY7C455
CY7C456
CY7C457
Pin Configurations (continued)
PQFP
Top View
D₂
D₁
D₀
XI
ENW
CKW
HF
E/F
XO/PAFE
Q₀
Q₁
Q₂
Q₃
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
7C455
34
7
7C456
33
8
7C457
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
D₁₃
D₁₄
D₁₅
D₁₆
D₁₇
FL/RT
MR
CKR
ENR
OE
Q₁₇/PG2/PE2
Q₁₆
Q₁₅
c455-3
Functional Description (continued)
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFOs to retransmit
the data. Read enable (ENR) and the write enable (ENW) must
both be HIGH during the retransmit, and then ENR is used to
access the data.When ENW is asserted, data is written into
the FIFO on the rising edge of the CKW signal. While ENW is
held active, data is continually written into the FIFO on each
CKW cycle. The output port is controlled in a similar manner
by a free-running read clock (CKR) and a read enable pin
(ENR). In addition, the CY7C455, CY7C456, and CY7C457
have an output enable pin (OE). The read (CKR) and write
(CKW) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 83.3 MHz are
achievable in the standalone configuration, and up to 83.3
MHz is achievable when FIFOs are cascaded for depth expan-
sion.
Depth expansion is possible using the cascade input (XI), cas-
cade output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
device. The FL pin of the first device is tied to V_SS.
The CY7C455, CY7C456, and CY7C457 provide three status
pins. These pins are decoded to determine one of six states:
Empty, Almost Empty, Less than or Equal to Half Full, Greater
than Half Full, Almost Full, and Full (see Table 1). The Almost
Empty/Full flag (PAFE) shares the XO pin on the CY7C455,
CY7C456, and CY7C457. This flag is valid in the standalone
and width-expansion configurations. In the depth expansion,
this pin provides the expansion out (XO) information that is
used to signal the next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to
either the read clock (CKR) or the write clock (CKW). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the CKR. The flags denoting
Half Full, Almost Full, and Full states are updated exclusively
by CKW. The synchronous flag architecture guarantees that
the flags maintain their status for some minimum time. This
time is typically equal to approximately one cycle time.
The CY7C455/6/7 uses center power and ground for reduced
noise. All configurations are fabricated using an advanced
0.65u CMOS technology. Input ESD protection is greater
than 2001V, and latch-up is prevented by the use of guard
rings.
Document #: 38-06003 Rev. *A
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